Ahmad Basri Abdul Ghani

Dissipation Factor Measurement of PILC Insulation at UHF

In this paper, dissipation factor measurement of Paper Insulated Lead Covered (PILC) cable insulation at ultra high frequency (UHF) is described. The material under test (MUT) is clamped between two copper sheets to form a capacitor, which is connected to the Advantest R3767CG vector network analyzer (VNA) to measure its input impedance at the resonant frequency. From the input impedance, the dissipation factor is calculated. The calculated values are then compared with data obtained from commercial system to validate the proposed method.

Diagnostic criteria based on the correlation of the measurement of DGA, moisture contents with PD & tan d in MV oil-filled underground cable

Gas-in-fluid analysis refers to dissolved gas analysis (DGA). DGA facilitates the observation of the by-products of the oil degradation through its environment, the insulating and pressurizing fluid. The three main degradation processes that generate gases are thermal degradation, partial discharge and arcing. The most significant gases generated from oil decomposition are hydrogen gas (H2), methane (CH4), ethane (C2H6), ethylene (C2H4) and acetylene (C2H2) [3]. The measurements of dissolve gas (DG) were made for the medium voltage oil-filled cable. Partial discharge (PD) measurement was done the MV oil-filled cable to determine the level of PD activities. The correlation of PD magnitude and DGA level were established to determine the severity of the results and for diagnostic purposes. The measurement of moisture contents in the insulating oil was made using Karl Fisher method.

Tan delta measurement of paper insulated laminates using capacitance method from 300kHz to 50MHz

Tan delta measurement of oil impregnated kraft paper extracted from paper insulated lead covered cables (PILC) has been performed using a parallel plate capacitor and a vector network analyzer (VNA) from 30 kHz to 50 MHz. The material under test (MUT) is flat and thin sample clamped between the capacitor plates and connected to the VNA to obtain its two port S parameters. The S parameter is converted into impedance to calculate the complex permittivity using Matlab program. Techniques used to overcome the air gap and stray capacitance was described. Measurement obtained using the proposed method was compared with the free space method to validate its accuracy. The percent difference is less than 5%.

Matlab and VHDL model of real time partial discharge detection using FPGA technology

This research involves evaluating the use of FPGA for the detection and counting of partial discharge (PD) signals in underground cables (XLPE cables). PD detection model was designed one using MATLAB and another using VHDL. The pulse signal from the cable was processed and counted using peak detector and FPGA technology. The peak detector placed inside the VHDL program when the program of PD detection model was designed using VHDL program. Then, the model designed was used for testing and validation. Both models are able detect the PD signals and the results obtained are similar.

VHDL implementation for measurement of the distance test distribution pattern of the Tri-Axial magnetic probe for the PD detection circuit system by using 3 GHz ADC and FPGA

This paper is purely a model to implement Partial Discharge (PD) detection in FPGA technology and then implement the VHDL modeled in FPGA technology for measurement of the distance test distribution pattern of the Tri-Axial magnetic probe using 3GHz ADC (ADC083000RB-Reference Board) and impulse generator. Partial discharge (PD) is a well known phenomenon that causes insulation degradation in cross linked polyethylene (XLPE) power cable and ultimately it will cause insulation failure. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA-Xilinx Virtex 5 ML501 Board) for the detection and counting of partial discharge signals in high voltage underground cable. The impulse signals at the input data have very fast rise time in the field can have a bandwith of about 200 - 600 MHz. The output signals of the combination 4 blocks (peak detector block, 64 bit BCD counter with reset block, reset automatic block and 64 bit BCD counter) is processed using reset automatic block and 64 bit latch block for keep output data in LCD to constant when the 64 bit BCD counter block is reset and return to zero again until update new data again. The combination of all blocks of PD detection circuit system is tested by using Xilinx ISE simulator and implemented by ISE Xilinx Synthesized Technology and Xilinx ISE Implement Design. The distance resolution measurement of magnetic field is shown in this paper.

Online partial discharge counting system using microcontroller PIC 16F877A and FPGA technology

This paper is purely a design circuit to implement Partial Discharge (PD) detection in FPGA technology using Xilinx ML405 board (Virtex 4) and real time ADC in microcontroller PIC 16F877A. The research involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in high voltage underground cable. The research also involve PCWH CCS C Compiler using C programming to run real time ADC in microcontroller PIC 16F877A. The impulse of PD signals is simulated by impulse generator in the lab simulation. The input data (PD signals) in high voltage underground cable have very fast rise time in the range of 1 ns to 2 ns in the real system. The speed clock of the real time ADC in microcontroller PIC is 20 MHz. This paper shows analysis data of ability of real time ADC in microcontroller PIC to measurement, detect and counting PD signal using FPGA technology. The combination of all blocks of PD detection circuit system is tested by using ISE Xilinx Synthesis Technology (XST) and ISE implementation. In the next stage, this method will be implemented on a next lab simulation scale using real PD signals that is detected by 3D magnetic probe sensor in real underground cable in laboratory for testing and validation before test in the real situation.

VHDL simulation of peak detector, 64 bit BCD counter and reset automatic block for PD detection system using FPGA

Currently, FPGA (Field Programmable Gate Array) technology is being widely used for accelerator control owing to its fast digital processing capability. This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 9.2i (Xilinx) and Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. The impulse signals will be processed, detected and counted using ADC with peak detector block, counter with reset block and reset automatic block.

VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in high voltage underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. The output signals of peak detector block, 64 bit BCD counter with reset block and reset automatic block is processed using reset automatic block and 64 bit latch block for keep output data in LCD to constant when the 64 bit BCD counter block is reset and return to zero again until update new data again. The combination of all blocks of PD detection circuit system is tested by using ISE simulator. In the next stage, this method will be implemented on a lab simulation scale for testing and validation.