Ahmad Ehteshamul Islam

Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation

Recent advances in experimental techniques (on-the- fly and ultrafast techniques) allow measurement of threshold voltage degradation due to negative-bias temperature instability (NBTI) over many decades in timescale. Such measurements over wider temperature range (-25degC to 145degC), film thicknesses (1.2-2.2 nm of effective oxide thickness), and processing conditions (variation of nitrogen within gate dielectric) provide an excellent framework for a theoretical analysis of NBTI degradation. In this paper, we analyze these experiments to refine the existing theory of NBTI to 1) explore the mechanics of time transients of NBTI over many orders of magnitude in time; 2) establish field dependence of interface trap generation to resolve questions regarding the appropriateness of power law versus exponential projection of lifetimes; 3) ascertain the relative contributions to NBTI from interface traps versus hole trapping as a function of processing conditions; and 4) briefly discuss relaxation dynamics for fast-transient NBTI recovery that involves interface traps and trapped holes.

A Comparative Study of Different Physics-Based NBTI Models

Different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data. Models that focus exclusively on hole trapping in gate-insulator-process-related preexisting traps are found to be inconsistent with direct experimental evidence of interface trap generation. Models that focus exclusively on interface trap generation are incapable of predicting ultrafast measurement data. Models that assume strong correlation between interface trap generation and hole trapping in switching hole traps cannot simultaneously predict long-time dc stress, recovery, and ac stress and cannot estimate gate insulator process impact. Uncorrelated contributions from generation and recovery of interface traps, together with hole trapping and detrapping in preexisting and newly generated bulk insulator traps, are invoked to comprehensively predict dc stress and recovery, ac duty cycle and frequency, and gate insulator process impact of NBTI. The reaction-diffusion model can accurately predict generation and recovery of interface traps for different devices and experimental conditions. Hole trapping/detrapping is modeled using a two-level energy well model.

On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy?

Negative bias temperature instability (NBTI) is studied in plasma (PNO) and thermal (TNO) Si-oxynitride devices having varying EOT. Threshold voltage shift (DeltaVT) and its field (EOX), temperature (T) and time (t) dependencies obtained from no-delay on-the-fly linear drain current (IDLIN) measurements are carefully compared to that obtained from charge pumping (CP). It is shown that thin and thick PNO and thin TNO devices show very similar NBTI behavior, which can primarily be attributed to generation of interface traps (DeltaNIT). Thicker TNO devices show different NBTI behavior, and can be attributed to additional contribution from hole trapping (DeltaNh) in pre-existing bulk traps. A physics based model is developed to explain the experimental results.

A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery

Reaction-Diffusion (R-D) framework for interface trap generation along with hole trapping in pre-existing and generated bulk oxide traps are used to model Negative Bias Temperature Instability (NBTI) in differently processed SiON p-MOSFETs. Time, temperature and bias dependent degradation and recovery transients are predicted. Long-time power law exponent of DC degradation and uniquely renormalized duty cycle and frequency dependent AC degradation data from a wide range of sources are shown to have universal features and a broad consensus across industry/academia. These universal features can also be predicted using the classical R-D framework.

Isolation of NBTI Stress Generated Interface Trap and Hole-Trapping Components in PNO p-MOSFETs

In this paper, a simple phenomenological technique is used to isolate the hole-trapping and interface trap generation components during negative bias temperature instability (NBTI) stress in plasma nitrided oxide (PNO) p-MOSFETs. This isolation methodology reconciles the apparent differences between experimentally measured NBTI power-law time exponents obtained by ultrafast on-the-fly IDLIN method, which are the ones obtained using slightly delayed but very long-time measurements, and the corresponding exponents predicted by the reaction-diffusion model. A systematic validation of the isolation technique is provided through degradation data taken over a broad range of operating conditions and a wide variety of PNO processes, to establish the robustness and uniqueness of the separation procedure.

Material Dependence of NBTI Physical Mechanism in Silicon Oxynitride (SiON) p-MOSFETs: A Comprehensive Study by Ultra-Fast On-The-Fly (UF-OTF) I DLIN Technique

An ultra-fast on-the-fly (UF-OTF) IDLIN technique having 1 mus resolution is developed and used to study gate insulator process dependence of NBTI in silicon oxynitride (SiON) p- MOSFETs. The nitrogen density at the Si-SiON interface and the thickness of SiON layer are shown to impact temperature, time, and field dependencies of NBTI. The plausible material dependence of NBTI physical mechanism is explored.

Exploring the Capability of Multifrequency Charge Pumping in Resolving Location and Energy Levels of Traps Within Dielectric

Multifrequency charge-pumping (MFCP) experiments have been used by many groups to profile the locations and the energy levels of bulk traps within high-kappa gate dielectric stack of MOS transistors. Since the measurements involve easy generalization of the classical CP technique, the interpretation of the data has sometimes been based on uncritical generalization of classical CP theory or a simplified numerical model that does not capture the complexity and nuances of the dynamics of occupation of dielectric traps. In this paper, we develop a rigorous numerical model of MFCP technique and encapsulate/interpret the results using an intuitively simple analytical formula. Consistent with some earlier reports, we observe that MFCP experiment scans a limited region of traps within the dielectric stack. Although the degree of trap response in MFCP is a (nonintuitive) function of parameters like rise/fall time, frequency, temperature, and pulse levels, we show that only a certain combination of parameters is sufficiently orthogonal to allow unambiguous back-extraction of the trap profile.

Gate Leakage vs. NBTI in Plasma Nitrided Oxides: Characterization, Physical Principles, and Optimization

Since nitrided oxides improve gate leakage at the expense of NBTI, one must optimize nitrogen concentration in oxinitride samples for reliable performance and reduced power dissipation. Here, we analyze wide range of NBTI stress data to develop a predictive model for gate leakage and first self-consistent model for field acceleration within R-D framework. This model anticipates a novel design diagram for co-optimization of leakage and NBTI for arbitrary nitrogen concentration and effective oxide thickness

Mobility degradation due to interface traps in plasma oxynitride PMOS devices

Mobility degradation due to generation of interface traps (Deltamueff(NIT)) is a well-known phenomenon that has been theoretically interpreted by several mobility models. Based on these analysis, there is a general perception that Deltamueff(NIT) is relatively insignificant (compared to Deltamueff due to ionized impurity) and as such can be safely ignored for performance and reliability analysis. Here, we investigate the importance of considering Deltamueff(NIT) for reliability analysis by analyzing a wide variety of plasma oxynitride PMOS devices using both parametric and physical mobility models. We find that contrary to popular belief this correction is fundamentally important for robust and uncorrupted estimates of the key reliability parameters like threshold-voltage shift, lifetime projection, voltage acceleration factor, etc. Therefore, in this paper, we develop a generalized algorithm for estimating Deltamueff(NIT) for plasma oxynitride PMOS devices and systematically explore its implications for NBTI-specific reliability analysis.

Characterization and estimation of circuit reliability degradation under NBTI using on-line I DDQ measurement

Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characterize and estimate the lifetime circuit reliability under NBTI degradation. Unlike conventional approaches, where a representative fMAX (maximum operating frequency) measurement from timing critical circuitry is used, we propose to utilize the standby circuit leakage IDDQ as a metric to detect and characterize temporal NBTI degradation in digital circuits. Compared to the fMAX based approach, the proposed IDDQ based technique benefits from lower test cost and improved capability of estimating reliability of complex circuitries such as ALUs and SRAM arrays. We have derived an analytical expression for circuit IDDQ from the analytical PMOS Vt degradation model (DeltaVt prop t1/6 ). The proposed model is verified with measurement data obtained from a test chip fabricated in 130 nm technology. Furthermore, we examine the possible applications of our proposed IDDQ based NBTI characterization. We show that the temporal degradation in static noise margin (SNM) of SRAM array and fMAX of random logic circuits are highly correlated to the IDDQ measurement, and this relationship can be used to predict long term circuit reliability.