Ahmad Zubair

Transport Properties of a MoS2/WSe2 Heterojunction Transistor and Its Potential for Application

This paper studies band-to-band tunneling in the transverse and lateral directions of van der Waals MoS2/WSe2 heterojunctions. We observe room-temperature negative differential resistance (NDR) in a heterojunction diode comprised of few-layer WSe2 stacked on multilayer MoS2. The presence of NDR is attributed to the lateral band-to-band tunneling at the edge of the MoS2/WSe2 heterojunction. The backward tunneling diode shows an average conductance slope of 75 mV/dec with a high curvature coefficient of 62 V(-1). Associated with the tunnel-diode characteristics, a positive-to-negative transconductance in the MoS2/WSe2 heterojunction transistors is observed. The transition is induced by strong interlayer coupling between the films, which results in charge density and energy-band modulation. The sign change in transconductance is particularly useful for multivalued logic (MVL) circuits, and we therefore propose and demonstrate for the first time an MVL-inverter that shows three levels of logic using one pair of p-type transistors.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

A Rational Strategy for Graphene Transfer on Substrates with Rough Features.

Graphene grown by chemical vapor deposition is transferred by a very simple, yet effective approach from the growth substrate onto substrates with rough features. This novel and facile method not only results in satisfactory transfer on substrates with terraces or grooves, but also gives rise to a successful result for uneven growth substrates.

Hot Electron Transistor with van der Waals Base-Collector Heterojunction and High-Performance GaN Emitter

Single layer graphene is an ideal material for the base layer of hot electron transistors (HETs) for potential terahertz (THz) applications. The ultrathin body and exceptionally long mean free path maximizes the probability for ballistic transport across the base of the HET. We demonstrate for the first time the operation of a high-performance HET using a graphene/WSe2 van der Waals (vdW) heterostructure as a base-collector barrier. The resulting device with a GaN/AlN heterojunction as emitter, exhibits a current density of 50 A/cm2, direct current gain above 3 and 75% injection efficiency, which are record values among graphene-base HETs. These results not only provide a scheme to overcome the limitations of graphene-base HETs toward THz operation but are also the first demonstration of a GaN/vdW heterostructure in HETs, revealing the potential for novel electronic and optoelectronic applications.

15-nm channel length MoS 2 FETs with single- and double-gate structures

We demonstrate single- and double-gated (SG & DG) field effect transistors (FETs) with a record source-drain length (L_S/D) of 15 nm built on monolayer (t_ch~0.7 nm) and 4-layer (t_ch~3 nm) MoS₂ channels using monolayer graphene as the Source/Drain contacts. The best devices, corresponding to DG 4-layer MoS₂-FETs with L_S/D=15 nm, had an I_on/I_off in excess of 10⁶ and a minimum subthreshold swing (SS_min.) of 90 mV/dec. at V_DS=0.5 V. At L_S/D=1 μm and V_DS=0.5 V, SS_min.=66 mV/dec., which is the best SS reported in MoS₂ FETs, indicating the high quality of the interface and the enhanced channel electrostatics.

Enhancement-mode single-layer CVD MoS2 FET technology for digital electronics

2D nanoelectronics based on single-layer (SL) MoS2 offers great advantages for ubiquitous electronics. With new device technology, highly uniform E-mode FETs using SL CVD MoS2 with positive VT, large mobility, excellent subthreshold swing are achieved. The integrated inverter shows excellent voltage transfer characteristic, close to rail-to-rail operation, high noise margin, large voltage gain (~45) and small static power. The combinational and sequential digital circuits shown here serve as a toolbox of building blocks for realizing wide range of digital circuitry.

Novel GaN trench MIS barrier Schottky rectifiers with implanted field rings

We demonstrate a novel GaN vertical Schottky rectifier with trench MIS structures and trench field rings. The new structure greatly enhanced the reverse blocking characteristics while maintaining a Schottky-like good forward conduction. The reverse leakage current improved beyond 104-fold and the breakdown voltage increased from 400 V to 700 V, while the low turn-on voltage (0.8 V) and on-resistance (2 mΩ·cm2) were retained. High-temperature operation up to 250 oC and fast switching performance were also demonstrated. This new device shows great potential for high-power and high-frequency applications.

High-yield large area MoS 2 technology: Material, device and circuits co-optimization

Two-dimensional electronics based on single-layer (SL) MoS2 offers significant advantages for realizing large-scale flexible systems owing to the ultrathin nature, good transport properties and stable crystalline structure of MoS2. However, the reported devices and circuits based on this material have low yield because of various variation sources inherent to the growth and fabrication technology. In this work, we develop a variation-aware design flow and yield model to evaluate the MoS2 technology and provide a guideline for the co-optimization of the material, devices and circuits. Test chips with various inverters and basic logic gates (such as NAND and XOR) are fabricated as demonstration of the close-to-unit yield of the proposed technology platform.