Ahmed A. Abou-Auf

A methodology for the identification of worst-case test vectors for logical faults induced in CMOS circuits by total dose

A new methodology was developed for the identification of the worst-case combination of irradiation and postirradiation test vectors. The methodology significantly simplifies total-dose testing of CMOS VLSI devices. It also provides more accurate assessment of failure levels for such devices. >

Research progress on a focal plane array ladar system using chirped amplitude modulation

The Army Research Laboratory is researching a focal plane array (FPA) ladar architecture that is applicable for smart munitions, reconnaissance, face recognition, robotic navigation, etc.. Here we report on progress and test results attained over the past year related to the construction of a 32x32 pixel FPA ladar laboratory breadboard. The near-term objective of this effort is to evaluate and demonstrate an FPA ladar using chirped amplitude modulation; knowledge gained will then be used to build a field testable version with a larger array format. The ladar architecture achieves ranging based on a frequency modulation/continuous wave technique implemented by directly amplitude modulating a near-IR diode laser transmitter with a radio frequency (rf) subcarrier that is linearly frequency modulated (chirped amplitude modulation). The diodes output is collected and projected to form an illumination field in the downrange image area. The returned signal is focused onto an array of optoelectronic mixing, metal-semiconductor-metal detectors where it is detected and mixed with a delayed replica of the laser modulation signal that modulates the responsivity of each detector. The output of each detector is an intermediate frequency (IF) signal resulting from the mixing process whose frequency is proportional to the target range. This IF signal is continuously sampled over a period of the rf modulation. Following this, a signal processor calculates the discrete fast Fourier transform over the IF waveform in each pixel to establish the ranges and amplitudes of all scatterers.

Line imaging ladar using a laser-diode transmitter and FM/cw radar principles for submunition applications

We describe the technical approach, component development, and test results of a line imager laser radar (ladar) being developed at the Army Research Laboratory (ARL) for smart munition applications. We obtain range information using a frequency modulation/continuous wave (FM/cw) technique implemented by directly amplitude modulating a near-IR diode laser transmitter with a radio frequency (rf) subcarrier that is linearly frequency modulated. The diodes output is collimated and projected to form a line illumination in the downrange image area. The returned signal is focused onto a line array of metal-semiconductor-metal (MSM) detectors where it is detected and mixed with a delayed replica of the laser modulation signal that modulates the responsivity of each detector. The output of each detector is an intermediate frequency (IF) signal (a product of the mixing process) whose frequency is proportional to the target range. This IF signal is continuously sampled over each period of the rf modulation. Following this, a N-channel signal processor based on field- programmable gate arrays (FPGA) calculates the discrete Fourier transform over the IF waveform in each pixel to establish the ranges to all the scatterers and their respective amplitudes. Over the past year, we constructed the fundamental building blocks of this ladar, which include a 3.5-W line illuminator, a wideband linear FM chirp modulator, a N-pixel MSM detector line array, and a N-channel FPGA signal processor. In this paper we report on the development and performance of each building block and the results of system tests conducted in the laboratory.

Worst-case test vectors for functional failure induced by total dose in CMOS microcircuits with transmission gates

Fault models for total-dose induced functional failure in CMOS microcircuits containing transmission gates have been developed for the automatic generation of worst-case test vectors. We use the circuits in the CMOSN Cell Library. This analysis is supported by SPICE simulation that utilizes experimentally extracted transistor parameters. We have also used our analysis to interpret data from a previous total-dose testing of a test chip designed using the CMOSN Cell Library and fabricated using 1 /spl mu/ technology.

Total-Dose Worst-Case Test Vectors for Leakage Current Failure Induced in Sequential Circuits of Cell-Based ASICs

We developed a methodology for identifying worst-case test vectors for leakage current failure induced in sequential circuits of cell-based ASICs induced by total-dose. This methodology is independent on the design tools and the process technology.

Research progress on a focal plane array ladar system using a laser diode transmitter and FM/cw radar principles

The Army Research Laboratory is developing scannerless ladar systems for smart munition and reconnaissance applications. Here we report on progress attained over the past year related to the construction of a 32x32 pixel ladar. The 32x32 pixel architecture achieves ranging based on a frequency modulation/continuous wave (FM/cw) technique implemented by directly amplitude modulating a near-IR diode laser transmitter with a radio frequency (rf) subcarrier that is linearly frequency modulated. The diodes output is collected and projected to form an illumination field in the downrange image area. The returned signal is focused onto an array of metal-semiconductor-metal (MSM) detectors where it is detected and mixed with a delayed replica of the laser modulation signal that modulates the responsivity of each detector. The output of each detector is an intermediate frequency (IF) signal (a product of the mixing process) whose frequency is proportional to the target range. This IF signal is continuously sampled over each period of the rf modulation. Following this, a N channel signal processor based-on field-programmable gate arrays calculates the discrete Fourier transform over the IF waveform in each pixel to establish the ranges to all the scatterers and their respective amplitudes. Over the past year, we have built one and two-dimensional self-mixing MSM detector arrays at .8 and 1.55 micrometers , designed and built circuit boards for reading data out of a 32x32 pixel array, and designed an N channel FPGA signal processor for high-speed formation of range gates. In this paper we report on the development and performance of these components and the results of system tests conducted in the laboratory.

Fault Modeling and Worst-Case Test Vectors for Logic Failure Induced by Total-Dose in Combinational Circuits of Cell-Based ASICs

We developed a methodology for identifying worst-case test vectors for logic faults induced by total dose in combinational circuits of cell-based ASICs. This methodology is independent of the design tools and the process technology.

Worst-Case Test Vectors for Logic Faults Induced by Total Dose in ASICs Using CMOS Processes Exhibiting Field-Oxide Leakage

We developed a cell-level fault model for logic failure induced in standard-cell ASIC devices exposed to total ionizing dose. This fault model is valid for CMOS process technologies that exhibit field-oxide leakage current under total dose. The fault model was represented at the cell level using hardware descriptive languages (HDL) such as VHDL or Verilog which consequently allowed for cell-level simulation of ASIC devices under total dose using functional simulation tools normally used within the HDL design flow of ASIC devices. We then developed a methodology to identify worst-case test vectors (WCTV) using commercially available automatic test pattern generation (ATPG) tools targeting the developed fault model. Finally, we experimentally validated the significance of using WCTV in total-dose testing of CMOS ASIC devices.

Fault Modeling and Worst-Case Test Vectors for Leakage Current Failures Induced by Total Dose in ASICs

We developed a cell-level fault model for leakage current failure of standard-cell ASIC devices exposed to total ionizing dose. This fault model is valid for CMOS process technologies that exhibit field-oxide leakage current under total dose. The fault model was represented using hardware descriptive languages which consequently allowed for cell-level simulation of ASIC devices under total dose using functional simulation tools normally used during the design flow of ASIC devices. However, the identification of worst-case test vectors using those tools using automatic test pattern generation (ATPG) tools targeting the fault model developed. This can lead to prohibitively long search time for WCTV in large ASIC devices. We developed an innovative search method based on genetic algorithms (GA) which made possible the identification of WCTV for large ASIC devices in very short time. Finally, we experimentally validated the significance of WCTV in total dose testing of ASIC devices.

Fault Modeling and Worst-Case Test Vectors of Sequential ASICs Exposed to Total Dose

We introduce a novel methodology for identifying worst-case test vectors for sequential circuits in ASIC devices exposed to total dose. Testing of sequential circuits requires the use of sequence of test vectors. Those test vectors were generated using cell-level fault models for failures induced by total dose. In this paper we focused on three types of failures: logic, leakage current, and delay failures. A novel cell-level fault model for delay failures induced by total dose is introduced in this paper. This methodology was validated using SPICE simulation as well as experimental results.