Ahmed A. Telba

Simulation technique for noise and timing jitter in phase locked loop

Timing jitter is a concern in high frequency timing circuits. Its presence can degrade system performance in many high-speed applications. In this paper, a new method for efficiently measuring timing jitter due to phase locked loops is described. Two important parameters, absolute jitter and cycle-to-cycle jitter, used to describe jitter performance can be analyzed. Simulation results for the measurement of jitter in phase locked loop using MATLAB SIMULINK are presented. The methodology described is also applicable to other types of clock generator and oscillators such as LC oscillators, as well as other kinds of noise source such as power supplies.

Jitter minimization in Digital Transmission using dual phase locked loops

Timing jitter is a concern in high frequency timing circuits. Its presence can degrade system performance in many high-speed applications. In this paper, a new method for minimization of timing jitter due to phase locked loops is described. The timing jitter can be minimized using two phase locked loops connected in cascade, where the first one has Voltage Controlled crystal Oscillator (VCXO) to eliminate the input jitter and the second is a wide band phase locked loop. Usually, RMS jitter is used to describe jitter performance of the system and that can be analyzed. Simulation results for the measurement of jitter in both phase locked loop using MATLAB Simulink are presented. The methodology described is also applicable to other types of clock generator.

Modeling and simulation of wideband low jitter frequency synthesizer

This paper presents modeling and simulation of a wideband low jitter frequency synthesizer. The proposed system uses two phase-locked loops (PLLs) connected in cascade. The first PLL uses a voltage-controlled crystal oscillator (VCXO) to eliminate the input jitter and the second one is a wideband PLL. One important advantage of using the proposed system is that it uses only one VCXO for multiple carrier frequencies, while reducing the jitter considerably. The MATLAB Simulink simulation results show that the jitter could be minimized while working at different carrier frequencies.

Modeling and simulation of volture piezoelectric energy harvester

Piezoelectric material is used as an active material to convert vibration energy into electrical output and so called piezoelectric energy harvesting. The harvesters dynamic model depends on several parameters such as physical dimensions, geometrical structure, mechanical and electrical properties of the piezoelectric material. The development of theoretical model for analysis and simulation is a complex task whereas complete information about these parameters is not available from the manufacturers datasheet. In this paper, the dynamic model parameters are identified experimentally to reduce the modeling effort and to develop easily the equivalent circuit for the energy harvester (Volture, V21BL). The validation is achieved by comparing the estimated power outputs using simulation model with the real time measured values. The obtained results affirmed the potential of the adopted approach for modeling and simulation.

Jitter and Phase-Noise in High Speed Frequency Synthesizer Using PLL

Jitter happens when data rates increase in high-speed input and output connections for data communications. Characterizing of jitter and measurement is challenge, jitter defined as the misalignment of edges in a sequence of data bits from their ideal positions. Misalignments can result in data errors, and raised bit error rate in digital communication. Tracking these errors over an extended period determines the system stability. Jitter can be due to deterministic and random phenomena, also referred to as systematic and non-systematic respectively. It is worth mentioning that the benefit of jitter is limited to applications using random number generation. There is hardly any other benefit from jitter. Phase noise and jitter are a very important issue when design a phase-locked and delay-locked loops. Different applications may have different emphasis on the jitter specifications. “Cycle-to-cycle” jitter refers to the time difference between two consecutive Cycles of a period signal. A RMS (root mean square) or peak-to-peak value is used to describe a random jitter. According to the noise sources, it can be classified as internal jitters, caused by the building blocks of PLLs and DLLs, and external jitters. Jitters in an Oscillator have been examined for almost half a century and still a hot topic.

DC MOTOR SPEED CONTROL USING FPGA

DC motor had been used in many applications. In some applications the control of DC Motor speed is a deal breaker. These applications require a very tight speed controlling to avoid serious problems. There are various ways to control the speed of motor. The process of developing any solution to a certain problem should goes through three steps. The first step is to simulate the problem and try to find the solution. The second one is to verify that your solution is really working before you try it on real-time problems. The last step is to validate your solution on real-time measurements. In this paper we studied the problem, analyzed it, and we found the solution and did simulation to check its outcomes. Our goals in this paper are to verify our solution and implement it using FieldProgrammable Gate Arrays (FPGAs). FPGAs must be programmed using Hardware Description Language (HDL). Xilinx had been used to control speed the simulation done using real time measurements using FPGA for step response of the system using MATLAB/SIMUKLINK and PSIM .

Real time measurements of hysteresis in a piezoelectric nanopositioner stage

This paper aims to develop a hysteresis model for a single axis piezoelectric nanopositioner stage at different operating points. The adopted methodology compares results based on the developed analytical simulation model using MATLAB with real time results using LabVIEW. The experimental results for real time measurements had been acquired for the piezoelectric nanopositioner stage using data acquisition system from National Instruments (NI). The experimental setup is described. The simulation and real time measurements results are compared to validate the adopted approach.

Experimental Investigation of Low‐Jitter and Wide‐Band Dual Cascaded PLL System

Jitter is a matter of great concern for high‐speed digital designers because of its ability to degrade the overall system performance. Designing a low‐jitter and wide‐band phase locked loop (PLL) system is of practical importance because of its application in high speed digital systems. This paper experimentally investigates a low‐jitter and wide‐band dual cascaded PLL system using a single crystal oscillator. The first PLL used in the system employs a voltage‐controlled crystal oscillator (VCXO) to eliminate the input jitter whereas the second PLL provides wide bandwidth. Field Programmable Gate Array (FPGA) is used to generate a jittered clock source which is then passed through the proposed system to achieve wide‐band and low‐jitter signal. Experimental results are presented to validate the proposed technique for different carrier frequencies.

Experimental results for low-jitter wide-band dual cascaded phase locked loop system

Jitter is a matter of great concern for high-speed digital designers because of its ability to degrade the overall; system performance. Designing a low-jitter and wide-band phase locked loop (PLL) system is of practical importance because of its application in high speed digital systems. This paper presents experimental results of a low-jitter wideband dual cascaded PLL system using a single crystal oscillator. The first PLL employs a voltage controlled crystal oscillator (VCXO) to eliminate the input jitter whereas the second PLL provides wide bandwidth. Field Programmable Gate Array (FPGA) is used to generate a jittered clock source which is then passed through the proposed system to achieve wideband and low-jitter signal. Experimental results are presented to validate the proposed technique for different carrier frequencies.

Behavioural Modelling and Simulation of Dual Cascaded PLL Based Frequency Synthesizer

In this paper, behavioural model of a dual cascaded phase locked loop (PLL) based frequency synthesizer is presented and the results are validated through SystemVision simulation using very high speed Integrated circuit hardware description language-analog mixed signal (VHDL-AMS). Dual cascaded PLL consists of a low jitter PLL employing a voltage controlled crystal oscillator (VCXO) followed by a wideband PLL employing normal voltage controlled oscillator (VCO). The advantage of using dual PLL in cascade configuration is that it provides very good performance in terms of low jitter as compared to a single PLL based frequency synthesizer. Simulation results obtained are in good agreement with the theoretical calculations.