Ahmed Awad

A fast process variation and pattern fidelity aware mask optimization algorithm

With the continuous shrinking of minimum feature sizes beyond current 193nm wavelength for optical micro lithography, the electronic industry relies on Resolution Enhancement Techniques (RETs) to improve pattern transfer fidelity. However, the lithographic process is susceptible to dose and focus variations that will eventually cause lithographic yield degradation. In this paper, a new algorithm is proposed to minimize the Edge Placement Error (EPE) and the process variability of the printed image. The algorithm is also adapted to reduce the computational time using a novel approach through minimizing the number of convolutions during lithography simulation time. Experimental results show that the proposed algorithm results in less average cost than the top three teams of ICCAD 2013 contest on the public benchmarks.

Comparative analysis of routing protocols for under-water wireless sensor networks

Underwater Sensor Networks (UWSNs) are significantly different from terrestrial sensor networks in the following aspects: low bandwidth, high latency, node mobility, high error probability, and 3-dimensional space. These new features bring many challenges to the network protocol design of UWSNs. The communication range of underwater wireless sensor networks (UWSNs) is limited, and the nodes are equipped with limited power battery whose replacement is expensive due to underwater harsh environment. Moreover, the networks including small number of nodes have communication problems for long ranges. In this paper, we evaluate the performance of three classical location-based routing protocols (namely, VBF, HH-VBF, and VBVA) for underwater wireless sensor networks in terms of three critical performance metrics for dynamic network topology. Our comparison includes energy consumption, end-to-end delay, and packet delivery ratio.

A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation

Aggressive Optical Proximity Correction (OPC) has been widely adopted in optical lithography to preserve circuit performance for sub-20nm technology nodes. However, complex mask patterns are output resulting in lower mask manufacturability and large computational time. In this paper, we propose a fast OPC algorithm in which intensity estimation during OPC is improved for better pattern fidelity and in which post processing to effectively improve mask manufacturability with preserving acceptable pattern fidelity is executed.

A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling

With the continuous shrinkage of advanced technology nodes into the sub-16-nm regime, optical proximity correction (OPC) is still the main stream to preserve acceptable wafer image quality under lithographic process variations in the foreseeable future. However, OPC is getting more aggressive to keep pace with advanced technology nodes. This results in complex mask solutions and long computation time. In this paper, we propose a novel-intensity-based OPC algorithm to find mask solutions with minimal edge placement error and process variability band area within a short computation time. This is achieved through exploiting a fast novel intensity estimation model with acceptable estimation accuracy to guide the OPC response including two-fragment shifting, corner hammering, and subresolution assist feature insertion for better convergence. Moreover, our algorithm is extended to satisfy the mask notch rule and reduce shot count for a lower mask manufacturing cost. The experimental results show that our algorithm outperforms recently published algorithms on the public benchmarks.

Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement

Optical Proximity Correction (OPC) is still nominated as a main stream in printing Sub-16 nm technology nodes in optical micro-lithography. However, long computation time is required to generate mask solutions with acceptable wafer image quality. Intensity Difference Map (IDM) has been recently proposed as a fast methodology to shorten OPC computation time with preserving acceptable wafer image quality. However, IDM has been evaluated only under a relatively relaxed Edge Placement Error (EPE) constraint of the final mask solution. Such an evaluation does not provide a satisfactory confirmation of the effectiveness of IDM if strict EPE constraints are imposed. In this paper, the accuracy of IDM is deeply analyzed to confirm its validity in terms of wafer image estimation accuracy along with its efficiency in shortening computation time. Thereafter, the stability of IDM accuracy against the increase in pattern area/density is confirmed. Finally, the regions suffering from lack of accuracy are analyzed for further enhancement. Experimental results show that congestion in the mask pattern forms a cardinal source of the lack of accuracy which is compensated through optimized selection of the kernels included in IDM.

A lithographic mask manufacturability and pattern fidelity aware OPC algorithm

Optical Proximity Correction (OPC) is still the main stream among Resolution Enhancement Techniques (RETs) for printing advanced technology nodes in optical lithography in the foreseeable future. However, to keep pace with the continuous shrinkage of feature dimensions, OPC algorithms are getting more aggressive to achieve acceptable pattern fidelity on the silicon wafer. This results in outputting complex mask patterns whose manufacturability is degraded. In this paper, we propose an intensity based OPC algorithm to improve mask manufacturability with preserving acceptable pattern fidelity following linearly interpolated intensity error model. Experimental results show the effectiveness of our algorithm on the public benchmarks.

Reducing Test Power for Embedded Memories

With the increased number of embedded memories in mobile devices, minimizing the test power becomes a serious concern, especially when parallel testing is applied. Battery will be lost and the entire System on Chip (SoC) is subjected to be damaged if the peak power exceeds the power constraint. This paper proposes a new scheme to reduce the peak power during embedded SRAMs testing in mobile devices. The scheme is based on (a) grouping different memories into clusters based on their word lengths, and (b)scheduling read and write operations in such a way that the consumed power is minimal. Simulation results of a case-of-study show that up to 60% in the peak power reduction can be achieved, at a cost of only one additional clock cycle test time

Detection and prevention of malicious cryptocurrency mining on internet-connected devices

As technology evolves, more and more devices are connected to the Internet. The popularity and increasing significance of cryptocurriences are drawing attention, and crybercriminals are trying to utilize the resources and steal the processing power of these devices. It is highly likely that there are billions of devices that are maliciously mining cryptocurrency for the benefit of a cybercriminal without noticing the damage they may be causing. This paper is proposed because there is a huge need to professionally defend and protect against the misuse of assets in order to avoid losses, both financially and operationally, and how it is possible to mitigate with this rising trend.