Ahmet Bindal

Thin films of mercury cadmium telluride for solar cell applications

Abstract Electroplated CdS/p-Hg1−x Cdx Te (MCT) thin-film solar cells with (1 - x) are evaluated and compared with electroplated CdS/p-CdTe devices. It is shown that the series resistance limitations commonly observed in CdS/p-CdTe devices can be appreciably reduced if p-CdTe is replaced by p-MCT. This is due to the lower resistivities attainable in p-MCT thin films which in turn reduce both bulk and contact resistances. The possiblity of bandgap control in MCT makes it an important candidate material for the production of high-efficiency tandem cells.

Hole traps in p‐type electrochemically deposited CdTe thin films

Deep level transient spectroscopy and photoluminescence measurements were performed for the first time on electrodeposited n‐CdS/p‐CdTe thin film solar cells. The observed levels were hole traps located at 0.2, 0.35, and 0.54 eV above the valence band. The nature of these hole traps can be attributed to the generation of Cd vacancies during the heat treatment step, which was used in device fabrication, to convert the as‐deposited n‐type films into p‐type layers.

Spice Modeling of Silicon Nanowire Field-Effect Transistors for High-Speed Analog Integrated Circuits

Vertical nanowire surrounding gate field-effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects and to achieve ultralow off current. This paper presents the fully depleted BSIMSOI modeling of low-power NMOS and PMOS SGFETs with 10 nm channel length and 2 nm channel radius, extraction of distributed device parasitics, and measuring the capabilities of these transistors for high-speed analog and RF applications. When biased with V ds = 0.5 V and V gs = 0.5 V at the active operating region, NMOS and PMOS SGFETs have 2 muA and 0.7 muA drain currents, 14 muA/V and 8 muA/V transconductances, 400 kOmega and 1.1 MOmega output resistances, 36 THz and 25 THz unity-current-gain cutoff frequencies, and 120 THz and 100 THz maximum frequency of oscillations, respectively. A single-stage CMOS SGFET amplifier dissipates 1.64 muW power and provides 500 GHz bandwidth with -6.5 gain and -24 dBm third-order intermodulation distortion tones for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. The large-signal operation of the amplifier with 1 V output swing exhibits 2.2 ps delay, 5.4 ps rise time, and 4.7 ps fall time while oscillating at 30 GHz. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next-generation very-large-scale integration (VLSI) technology.

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

This exploratory study on vertical, undoped silicon nanowire transistors shows less power dissipation with respect to the bulk and SOI MOS transistors while yielding comparable performance. The design cycle starts with determining individual metal gate work functions for each nMOS and pMOS transistor as a function of wire radius to produce a 300 mV threshold voltage. Wire radius and effective channel length are both varied until a common body geometry is determined for both nMOS and pMOS transistors to limit off currents under 1 pA while producing highest on currents. DC characteristics of the optimum n and p-channel transistors such as threshold voltage roll-off, DIBL and subthreshold slope are measured; simple CMOS gates including an inverter, 2- and 3-input nand, nor, and xor gates, and full adder are built to measure the transient performance, power dissipation and layout area. Postlayout simulation results indicate that the worst case delay for a full adder circuit is 8.5 ps at no load and increases by 0.15 ps/aF; worst case power dissipation of the same circuit is 23.6 nW at no load and increases by 4.04 nW/aF at 1 GHz. The full adder layout area occupies approximately 0.11 mum2

The design of a new spiking neuron using dual work function silicon nanowire transistors

A new spike neuron cell is designed using vertically grown, undoped silicon nanowire transistors. This study presents an entire design cycle from designing and optimizing vertical nanowire transistors for minimal power dissipation to realizing a neuron cell and measuring its dynamic power consumption, performance and layout area. The design cycle starts with determining individual metal gate work functions for NMOS and PMOS transistors as a function of wire radius to produce a 300 mV threshold voltage. The wire radius and effective channel length are subsequently varied to find a common body geometry for both transistors that yields smaller than 1 pA OFF current while producing maximum drive currents. A spike neuron cell is subsequently built using these transistors to measure its transient performance, power dissipation and layout area. Post-layout simulation results indicate that the neuron consumes 0.397 µW to generate a +1 V and 1.12 µW to generate a −1 V output pulse for a fan-out of five synapses at 500 MHz; the power dissipation increases by approximately 3 nW for each additional synapse at the output for generating either pulse. The neuron circuit occupies approximately 0.27 µm2.

The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits

This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication difficulties and then determines a common device geometry to produce an OFF current smaller than 1 pA for each transistor. Once an optimum wire radius and effective channel length is determined, DC characteristics including threshold voltage roll-off, drain-induced barrier lowering and sub-threshold slope of each transistor are measured. Simple CMOS gates such as an inverter, two- and three-input NAND, NOR and XOR gates and a full adder, composed of the optimum NMOS and PMOS transistors, are built to measure transient performance, power dissipation and layout area. Simulation results indicate that worst-case transient time and worst-case delay are 1.63 and 1.46 ps, respectively, for a two-input NAND gate and 7.51 and 7.43 ps, respectively, for a full adder for a fan-out of six transistor gates (24 aF). Worst-case power dissipation is 62.1 nW for a two-input NAND gate and 118.1 nW for a full adder at 1 GHz for the same output capacitance. The layout areas are 0.0066 µm2 for the two-input NAND gate and 0.049 µm2 for the full adder circuits.

Design of Next Generation Amplifiers Using Nanowire FETs

Vertical nanowire SGFETs (Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10㎚ channel length and a 2㎚ channel radius. The amplifier dissipates 5㎼ power and provides 5㎔ bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40㏈m and -52㏈m, respectively, and the 3rd order intermodulation is -24㏈m for a two-tone input signal with 10㎷ amplitude and 10㎓ frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

On the nature of the silicon activation efficiency in liquid‐encapsulated Czochralski‐grown GaAs by photoluminescence

The shallow defect evolution in Si‐implanted and ‐annealed liquid‐encapsulated Czochralski‐grown GaAs is investigated by photoluminescence experiments. Three major emission lines are found. The first emission line located at 1.492 eV corresponds to the SiGa‐CAs radiative recombination. The remaining two lines located at 1.44 and 1.40 eV are shown to correspond to GaI‐SiAs and VAs‐SiAs radiative recombinations, respectively. The effects of these three shallow centers on the silicon activation efficiency are discussed with respect to different annealing and implantation conditions.

Static NMOS circuits for crossbar architectures using silicon nano-wire technology

This study shows the design and analysis of static NMOS gates composed of silicon nano-wire surrounding gate pull-down NMOSFETs (SGFETs) and p-type pull-up resistors as the primary building blocks to form high density circuits. The device geometry and doping concentration of NMOS transistors and p-type resistors are varied until the lowest noise margin and standby power dissipation are obtained for an inverter. The optimum NMOS transistor and p-type resistor configurations are subsequently used to build various NOR-type static logic gates including a full adder to evaluate the transient performance, power consumption and layout area of each gate. A power-saving technique that replaces the p-type pull-up resistor with a p-type MESFET is also investigated for large-scale logic strings. Simulation results indicate that the worst-case rise and fall delays for a full adder are 130 ps and 90 ps at no capacitive load, and increase by 27.5 ps and 10 ps per fan-out, respectively. The worst-case power dissipation for the same circuit is 186.4 ?W. The full adder circuit occupies approximately a 25 ?m2 area if laid out conventionally and 36 ?m2 if laid out on a crossbar platform. Compared to same feature size conventional CMOS technologies, silicon nano-wire technology offers simplicity in interconnect routing and reduction in the layout area for similar circuit performance.

Observation of recombination center‐assisted tunneling current in Al(Cu)‐penetrated PtSi Schottky barrier diodes

The electrical transport characteristics of Al(Cu)‐penetrated PtSi Schottky barrier diodes were investigated. It has been observed for the first time that diodes with Al(Cu) penetration show a multistep recombination center‐assisted tunneling current in the forward direction instead of a thermionic emission current over the Al(Cu) alloy barrier. According to this electron transport mechanism an electron tunnels through a series of closely packed local recombination centers in the depletion region to traverse from the semiconductor to the metal side. When the penetrated diodes are reverse biased, Zener tunneling becomes the dominant conduction mechanism in the reverse direction. Al(Cu) penetration in PtSi Schottky barrier diodes produces high leakage currents and unpredictable turn‐on voltage characteristics which result in various design problems in logic circuits.