Ahmet T. Erdogan

Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC

This paper describes the architecture of our dynamically reconfigurable network-on-chip (NoC) architecture that has been proposed for reconfigurable multiprocessor system-on-chip (MPSoC), as a solution to the increased communication needs, low silicon cost, quality of service and scalability of network in mind. The novelty of the proposed NoC lies in the fact that it dynamically configures itself with respect to routing, switching and data packet size with the changing communication requirements of the system at run time, thus aiming to provide low latency, low power and high data throughput. Simulation results and a prototype implementation of the idea have shown its efficiency when simulated under different traffic condition at a negligible area overhead

FPGA implementation of K-means algorithm for bioinformatics application: An accelerated approach to clustering Microarray data

The Microarray is a technique used by biologists to perform many genome experiments simultaneously, which produces very large datasets. Analysis of these datasets is a challenge for scientists especially as the number of genome databases is increasing rapidly every year. K-means clustering is an unsupervised data mining technique used widely by bioinformaticians to analyze Microarray data. However, K-means can take between a few seconds to several days to process Microarray data depending on the size of these datasets. This puts a limit on the complexity of biological problems which can be asked by bioinfomaticians, and hence may result in an incomplete solution to the problem. In order to overcome such problems, we propose a highly parallel hardware design to accelerate the K-means clustering of Microarray data by implementing the K-means algorithm in Field Programmable Gate Arrays (FPGA). Our implementation is particularly suitable for server solution as it allows for processing many different datasets simultaneously. We have designed, and implemented five k-mean cores on Xilinx Virtex4 XC4VLX25 FPGA, and tested them on a sample of real Yeast Microarray data. Our design achieved about 51.7× speed-up when compared to a software model while being 206.8× more energy efficient.

An ILP formulation for task mapping and scheduling on multi-core architectures

Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory architecture, and task mapping and scheduling. This paper presents an integer linear programming formulation for the task mapping and scheduling problem. The technique incorporates profiling-driven loop level task partitioning, task transformations, functional pipelining, and memory architecture aware data mapping to reduce system execution time. Experiments are conducted to evaluate the technique by implementing a series of DSP applications on several multi-core architectures based on dynamically reconfigurable processor cores. The results demonstrate that the proposed technique is able to generate high-quality mappings of realistic applications on the target multi-core architecture, achieving up to 1.3× parallel efficiency by employing only two dynamically reconfigurable processor cores.

Low-Power H.264 Video Compression Architectures for Mobile Communication

This paper presents a method to reduce the computation and memory access for variable block size motion estimation (ME) using pixel truncation. Previous work has focused on implementing pixel truncation using a fixed-block-size (16 times 16 pixels) ME. However, pixel truncation fails to give satisfactory results for smaller block partitions. In this paper, we analyze the effect of truncating pixels for smaller block partitions and propose a method to improve the frame prediction. Our method is able to reduce the total computation and memory access compared to conventional full-search method without significantly degrading picture quality. With unique data arrangement, the proposed architectures are able to save up to 53% energy compared to the conventional full-search architecture. This makes such architectures attractive for H.264 application in future mobile devices.

Highly Parameterized K-means Clustering on FPGAs: Comparative Results with GPPs and GPUs

K-means clustering has been widely used in processing large datasets in many fields of studies. Advancement in many data collection techniques has been generating enormous amount of data, leaving scientists with the challenging task of processing them. Using General Purpose Processors or GPPs to process large datasets may take a long time, therefore many acceleration methods have been proposed in the literature to speed-up the processing of such large datasets. In this work, we propose a parameterized Field Programmable Gate Array (FPGA) implementation of the Kmeans algorithm and compare it with previous FPGA implementation as well as recent implementations on Graphics Processing Units (GPUs) and with GPPs. The proposed FPGA implementation has shown higher performance in terms of speed-up over previous FPGA GPU and GPP implementations, and is more energy efficient.

R3TOS: A reliable reconfigurable real-time operating system

The foundations for building the first Reliable Reconfigurable Real-Time Operating System (R3TOS) are presented. The main objective of R3TOS is to create an infrastructure for coordinately executing specialized hardware tasks upon a reconfigurable FPGA device, achieving the necessary flexibility for both gaining system performance (true hardware multitasking) and tolerating the occurring faults in the underlying chips silicon at runtime (true fault removal from system). R3TOS is aimed at easing the development of FPGA-based high-performance demanding reliable applications by hiding the complexity of these devices, promoting their use by the whole engineering community.

A low-power and domain-specific reconfigurable FFT fabric for system-on-chip applications

A low-power dynamic reconfigurable FFT fabric is proposed in this paper. The architecture is served as a scalable IP core, which is suitable for system on chip applications. The system can be configured as 16, 32, 64, 128, 256, 512 and 1024-point FFT. Compared with a conventional ASIC FFT processor, this FFT fabric is characterized by having dynamic reconfigurability while incurring only a 12 /spl sim/ 19% increase in energy consumption, and requiring 14% more area than a 1024-point non-reconfigurable FFT fabric. On the other hand, compared with a FFT processor which is mapped onto a general purpose reconfigurable architecture, it has 30 /spl sim/ 94% less energy consumption.

A novel bus encoding scheme from energy and crosstalk efficiency perspective for AMBA based generic SoC systems

Interwire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC systems. Elimination or minimization of such faults is crucial to the performance and reliability of SoC designs. This paper presents a new on-chip bus encoding scheme targeting high performance generic SoC systems. In addition to its efficiency in terms of power, the scheme reduces delay faults by completely eliminating the most critical type of crosstalk coupling that causes three adjacent wires to undergo Miller-like transition simultaneously. The paper describes the technique, its implementation (using the widely adopted AMBA-AHB SoC bus standard) and provides results indicating between 24% to 38% energy saving for systems implemented in 0.18 /spl mu/m CMOS technology.

ESPACENET: A Framework of Evolvable and Reconfigurable Sensor Networks for Aerospace–Based Monitoring and Diagnostics

There is an increasing need to develop flexible, reconfigurable, and intelligent multi-spacecraft sensing networks for aerospace-based monitoring and diagnostics. Technical advancements in ad hoc networking, MEMS devices, low-power electronics, adaptive and reconfigurable hardware, micro-spacecraft, and micro-sensors have enabled the design and development of such highly integrated space wireless sensor networks. This paper proposes the framework for an evolvable sensor network architecture, investigated as part of the ESPACENET project, collocated at the University of Edinburgh, Essex, Kent and Surrey. The aim is to design a flexible and intelligent embedded network of reconfigurable piconodes optimised by a hierarchical multi-objective algorithm. Although the project is targeted at aerospace applications, the same intelligent network can be used for many earth bound applications such as environmental and medical diagnostics

A novel application specific network protocol for wireless sensor networks

The recent interest in wireless sensor networks (WSN) has led to the emergence of many application specific communication protocols which must be energy-efficient. Among those protocols developed for WSN, LEACH (low energy adaptive clustering hierarchy) protocol is one of the most popular protocols. In this paper, a novel application specific energy efficient protocol based on LEACH is presented, combining a cluster based architecture and multiple-hop routing. Multi-hop routing is utilized for inter-cluster communication between cluster heads and the base station, instead of direct transmission in order to minimize transmission energy. Besides, this protocol adds some mechanisms to CSMA/CD (carrier sense multiple access with collision detection) so as to avoid collisions, instead of using other more complicated MAC protocols. Simulation results, compared with LEACH, demonstrate that our novel protocol can reduce energy consumption and hence prolong the lifetime of WSN.