Ahsan Aziz

High-Throughput FPGA-Based QC-LDPC Decoder Architecture

We propose without loss of generality strategies to achieve a high-throughput FPGA-based architecture for a binary Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) code based on a circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM) providing a multi-fold throughput gain. Splitting of the node processing algorithm enables us to achieve pipelining of blocks and hence layers. By partitioning the PCM into not only layers but superlayers we derive an upper bound on the two-layer pipelining depth for the compact representation. To validate the architecture, a decoder for the IEEE 802.11n (2012) QC-LDPC is implemented on the Xilinx Kintex-7 FPGA with the help of the FPGA IP compiler available in the NI LabVIEW Communication System Design Suite (CSDS). It offers an automated and systematic compilation flow where an optimized hardware implementation from the LDPC algorithm was generated, achieving an overall throughput of 608Mb/s (at 260MHz). As per our knowledge this is the fastest implementation of the IEEE 802.11n QC-LDPC decoder using an algorithmic compiler.

Robust beamforming with channel uncertainty for two-way relay networks

This paper presents the design of a robust beamforming scheme for a two-way relay network, composed of one multi-antenna relay and two single-antenna terminals, with the consideration of channel estimation errors. Given the assumption that the channel estimation error is within a certain range, we aim to minimize the transmit power at the multi-antenna relay and guarantee that the signal to interference and noise ratios (SINRs) at the two terminals are larger than a predefined value. Such a robust beamforming matrix design problem is formulated as a non-convex optimization problem, which is then converted into a semi-definite programming (SDP) problem by the S-procedure and rank one relaxation. The robust beamforming matrix is then derived from a principle eigenvector based rank-one reconstruction algorithm. We further propose a hybrid approach based on the best-effort principle to improve the outage probability performance, which is defined as the probability that one of two resulting terminal SINRs is less than the predefined value. Simulation results are presented to show that the robust design leads to better outage performance than the traditional non-robust approaches.

Linearized Robust Beamforming for Two-Way Relay Systems

In beamforming, channel state information (CSI) is used to design the beamforming vector (or matrix). Since in a practical system the CSI always needs to be estimated, channel estimation (CE) errors are inevitable, which could severely affect the performance of a beamforming scheme. In this paper, we present a novel beamforming method for two-way relay (TWR) systems that is robust against CE errors. The proposed method obtains a sub-optimal solution for the associated non-convex robust optimization problem by solving a set of closed-form linear equations. Simulations show a considerable performance gain over the rank-one relaxation-based semidefinite programming (SDP) solutions, especially for the cases where the relaxed problem becomes infeasible. In addition, there is significant reduction in complexity, making this method very attractive for practical implementation.

Analog compressed sensing for RF propagation channel sounding

Massively broadband® RF channel sounding is severely constrained by the sampling rates required for analog to digital conversion. Analog compressed sensing (CS) techniques based on Xampling have demonstrated the ability to lower sampling rates far below the Nyquist rate. Here, we show attributes of the multipath channel sounding problem appear to be well suited to CS approaches for reducing measurement acquisition time while simultaneously estimating time delays, multipath amplitudes, and angles of arrival. This paper presents results of the fusion of CS with modern channel sounding. We show measured propagation data from 60 GHz field trials and note the channel sparsity in time and space. We then propose an architecture for the first massively broadband CS channel sounder based on the Xampling framework (which we call the Channel Sounding Xampler) to exploit the sparsity, and we use field measurements to explore tradeoffs between analog and digital signal processing to perform channel impulse response (CIR) parameter estimation in real time. We also offer conceptual approaches for the Channel Sounding Xampler designed to trade off analog and digital components with the goal of improving CIR acquisition at sub-THz frequencies.

Physical layer authentication using controlled inter symbol interference

Spectrum security and enforcement is one of the major challenges that need to be addressed before cognitive radios (CR) can be widely deployed for opportunistic spectrum sharing. One of the mechanisms needed to carry out spectrum enforcement is the authentication or identification of transmitters. We propose a novel scheme for authenticating transmitters at the physical layer called partial response signaling with authentication (PRSA). Our results indicate that PRSA is superior to the prior art in terms of detection performance.

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation

The increasing data rates expected to be of the order of Gb/s for future wireless systems directly impact the throughput requirements of the modulation and coding systems of the physical layer. In an effort to design a suitable channel coding solution for 5G wireless systems, in this brief we present two approaches to improve the throughput of a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture. While providing an algorithmic method to enhance parallel processing within the decoder in the first approach, in the second approach we apply the decoder architecture to achieve another highly-parallel architecture. We have successfully validated the second approach to get a 2.48Gb/s QC-LDPC decoder implementation operating at 200MHz on the Xilinx Kintex-7 FPGA in the NI USRP-2953R. For rapid-prototyping our research findings, the high-level description of the entire decoder was translated to a Hardware Description Language (HDL), namely VHDL, using the algorithmic compiler in the National Instruments LabVIEW™ Communication System Design Suite (CSDS™). As per our knowledge, at the time of writing this paper, this is the fastest FPGA-based implementation of a standard compliant QC-LDPC decoder on a USRP using an algorithmic compiler.

Full Dimension MIMO (FD-MIMO): Demonstrating Commercial Feasibility

Massive multi-input multi-output (MIMO) is shown to significantly increase spectral efficiency by exploiting a large number of antennas to support high-order multiuser MIMO. In 3GPP Release-13, a full-dimension MIMO (FD-MIMO) technology was introduced to address practical aspects for massive MIMO in cellular systems; extensive simulations show 2–4 times capacity gain compared with current LTE systems. FD-MIMO has been identified as one of the key 5G technologies and is being continuously improved in 3GPP new radio standards. However, several practical challenges such as interference mitigation among MIMO streams for a large number of users with limited channel feedback, hardware limitations, such as calibration errors that limit the precoding capabilities need to be addressed carefully. A proof of concept (PoC) base-station and user equipment (UE) prototype has been designed to validate the potential of FD-MIMO technology and demonstrate commercial implementation feasibility. In this paper, we present theory and architecture behind an FD-MIMO prototype and share the field test results with LTE-based UEs in a multi-user MIMO setup. We also analyze the impact of transmitter and receiver calibration errors on the performance of the FD-MIMO system.

Algebraic method for optimal beamforming in two-way relay systems with analog network coding

The problem of optimal beamforming for two-way relay (TWR) systems with perfect channel state information (CSI) that use analog network coding (ANC) is reduced to a pair of algebraic equations in two variables that can be solved very inexpensively using the conjugate gradient algorithm. The solution has greatly reduced complexity compared to previous optimal solutions via semidefinite programming (SDP). Together with a previously-designed linearized algorithm for beamforming in the robust (imperfect CSI) case, it provides a high-performance, low-complexity robust beamforming solution for 2-way relays.

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

Link quality analysis in the presence of blockages for analog beamformed mm-wave channel

Future systems of the 5th generation are slated to use the mm-wave bands due to the large slices of bandwidth available at those frequencies. Relative to the contemporary microwave bands, to compensate for the harsh propagation conditions, highly directional communication using beamforming methods is necessary to achieve a level of reliable communication, however minimal. Due to the fragile nature of directional communication (especially in dense urban environments or high mobility environments), there is a need to understand the effect of blockages on the system performance. Blockages on links (post beamforming) necessitate time and power expensive mechanisms such as beam adaptation or even re-training the beam setup. In systems aiming for less than 1ms latency, this can be impracticable. While the channel modeling effort for mm-wave bands is underway, the nature of environmental blockages for outdoor cellular communications is still not well understood. In this paper, to study the impact of blockages, in addition to the real-world challenges of mm-wave communications, we propose a hierarchical blockage model where, an arbitrary path (LOS or NLOS) undergoes a blockage with probability p (model parameter) independent of the other paths. Our results show that, even in the event of an unblocked LOS, there is a notable degradation in the received SNR. We also show that the increase in the path loss due to a severe level of environmental blockages is about 15dB relative to environments with a low level of blockages, for a distance of 150m which is approximately the envisioned cell radius for 5G cellular systems. Thus implying that, the range of reliable communication shrinks in the presence of environmental blockages.