Ajay V. Bhatt

The Intel Geneseo Project

Summary form only given. Moores law has enabled the current trend toward multi-core computing that is dramatically increasing performance and power efficiency. I/O interconnects are on a similar growth path of increasing performance and efficiency. As computing requirements become more complex, new strategies evolve to provide the performance necessary for data-and calculation-intensive applications. A growing such strategy is the use of specialized accelerators to enhance the performance of specific tasks or functions. Broadly speaking, an accelerator is a device that attaches to a computing system, providing optimal performance at reduced cost and/or power for a specialized task. Examples of emerging applications for which accelerators may be suitable are photorealistic graphics, financial simulation, and climate modeling. The development of specialized application accelerators is happening today. However, they do not share a common attach point, and have no common architecture or programming model. An industry framework that economically and efficiently enables specialized acceleration is highly desirable. This talk will focus on a new architectural framework for the attached application accelerators called Geneseo. The talk will provide an overview of the Geneseo interconnect and software architecture and provide insight in to proposed improvements in available bandwidth, latency, efficiency and software interface.