Ajith Pasqual

FPGA-based compact and flexible architecture for real-time embedded vision systems

A single-chip FPGA implementation of a vision core is an efficient way to design fast and compact embedded vision systems from the PCB design level. The scope of the research is to design a novel FPGA-based parallel architecture for embedded vision entirely with on-chip FPGA resources. We designed it by utilizing block-RAMs and IO interfaces on the FPGA. As a result, the system is compact, fast and flexible. We evaluated this architecture for several mid-level neighborhood algorithms using Xilinx Virtex-2 Pro (XC2VP30) FPGA. Our algorithm uses a vision core with a 100 MHz system clock which supports image processing on a low-resolution image of 128×128 pixels up to 200 images per second. The results are accurate. We have compared our results with existing FPGA implementations. The performance of the algorithms could be substantially improved by applying sufficient parallelism.

Towards realtime handheld MonoSLAM in dynamic environments

Traditional monoSLAM assumes stationary landmarks making it unable to cope up with dynamic environments where moving objects are present in the scene. This paper presents the parallel implementation of monoSLAM with a set of independent EKF trackers where stationary features and moving features are tracked separately. The difficult problem of detecting moving points from a moving camera is addressed by the epipolar constraint computed by using the measurement information already available with the monoSLAM algorithm. While doing so SLAM measurement outlier rejection is also performed. Results are presented to verify and highlight the advantages of our approach over traditional SLAM.

Use of multiple visual features for object tracking

In this paper we present a method of using multiple visual attributes (features) that are present in moving objects for carrying out object tracking, by way of feature substitution. The proposed method, in principle, can make use of many visual cues available from a scene such as texture, color, velocity (monocular features) and disparity, vergence (binocular features). For the present experiments we make use of 3 features, namely, texture, optical flow and color as the main visual features and defocus of objects (blur) as supportive feature. At any instance, tracking is carried out using only one feature and this feature is monitored closely for failures. The feature is substituted with another suitable feature only upon the failure or high uncertainty of the current features. In case of tracking using texture alone, we make use of a histogram based technique called Histogram Intersection Value. This technique is not only computationally simple but provides very good results whenever texture is suitable for tracking. Experimental results with real image sequences show the validity of the proposed method.

HLS approach in designing FPGA-based custom coprocessor for image preprocessing

Control the data flow between device interfaces, processing blocks and memories in a vision system is complex in hardware implementation. In the research, high-level synthesis tool is used to design, implement and test the vision system within the context of required control, synchronization, and parameterization on a processor based platform. In addition, both HLS tools and HDL were used for the development of the processing cores, and the performance of the two versions were analyzed and compared. The operational structures of benchmarked vision core consist of custom vision coprocessor with efficient memory and bus interfaces. The performance properties such as accuracy, throughput and efficiency are measured and presented. Xilinx XC5VLX110T FPGA, has been used for prototype the hardware platforms. According to results, without any complex optimizations, pipeline length and resource utilization was achieved compared with the HDL counterpart. Our image pre-processing architecture which was implemented using HLL is faster than the optimized software implementation on an Intel Core 2 Duo GPU. The development time using AccelDSP was roughly five times shorter than using Verilog. Therefore, the availability of competent high-level synthesis tools will significantly reduce costs and design constraints in embedded image-processing implementations on FPGA.

Real time all intra HEVC HD encoder on FPGA

Higher compression efficiency in HEVC encoders comes with increased computational complexity, making real time encoding of high resolution videos a challenging task. This challenge can be addressed by software, yet hardware solutions are more appealing due to their superior performance and low power consumption. This paper presents an FPGA based hardware implementation of an all intra HEVC encoder, which can encode 8 bits per sample, 1920×1080 resolution, 30 frames per second raw video, that is viable in real time even at low operating frequencies. A major obstacle to real time encoding in available architectures is the dependency created by reference generation. Moreover, each coding unit (CU) has to be processed in multiple configurations to determine the most efficient split and prediction mode representation, based on the bit stream generated. We propose a new three stage architecture to reduce these dependencies and increase parallelism. Feedback needed for CU split and prediction direction decision from binarization is avoided by a Hadamard based early decision method. Feedback constrained coefficient and reconstruction derivation module exploits several optimization techniques. All modules can operate at 200 MHz and the encoder can achieve real time encoding with a minimum operating frequency of 140 MHz. The design consumes 83K LUTs, 28K registers, and 34 DSPs when implemented on Xilinx Zynq ZC706.

High performance parallel packet Classification architecture with Popular Rule Caching

Packet Classification is the enabling function for many Internet functions like QoS and Security. In this paper we propose a Classification engine architecture which exploits parallelism to increase throughput. The architecture also make use of the Temporal locality observed in Internet traffic positively by employing Popular Rule Caching mechanism to increase the classification throughput. We also introduce Rule Splitting mechanism to increase the accuracy of the rule caching mechanism. Simulation results revealed that the architecture is capable of achieving a throughput of more than 200Gbps when lowest amount of temporal locality is present for worst case packet size of 40 bytes.

A generalized preprocessing and feature extraction platform for scalp EEG signals on FPGA

Brain-computer interfaces (BCIs) require real-time feature extraction for translating input EEG signals recorded from a subject into an output command or decision. Owing to the inherent difficulties in EEG signal processing and neural decoding, many of the feature extraction algorithms are complex and computationally demanding. Presently, software does exist to perform real-time feature extraction and classification of EEG signals. However, the requirement of a personal computer is a major obstacle in bringing these technologies to the home and mobile user affording ease of use. We present the FPGA design and novel architecture of a generalized platform that provides a set of predefined features and preprocessing steps that can be configured by a user for BCI applications. The preprocessing steps include power line noise cancellation and baseline removal while the feature set includes a combination of linear and nonlinear, univariate and bivariate measures commonly utilized in BCIs. We provide a comparison of our results with software and also validate the platform by implementing a seizure detection algorithm on a standard dataset and obtained a classification accuracy of over 96%. A gradual transition of BCI systems to hardware would prove beneficial in terms of compactness, power consumption and much faster response to stimuli.

Minimal Invasive Headband for Brain Computer Interfacing and Analysis

An electroencephalogram (EEG) instrument has been successfully developed and tested for capturing, visualizing and recording brain activity using both active and passive electrodes. The key idea is to capture a noise free composite brain wave and separate out its constituent components, namely delta, theta, alpha, beta and gamma. The system consists of three functional parts including EEG signal capturing, Digitizing and wireless transmission and PC end software for visualizing and post processing. EEG signal capturing part consists of electrodes, amplification circuit for each channel and Right Leg Driver circuit to eliminate 50 Hz power line noise. The digital band pass filters and the 50 Hz notch filter which confiscates any residual noise components are built in the PC software. Battery power and wireless communication gives the sovereignty to the user to move around with the system while being monitored. The test results showed that system could meet the demands in researching various kinds of EEG related experiments in laboratory.

Layered Depth Image Based HEVC Multi-view Codec

Multi-view video has gained widespread popularity in the recent years. 3DTV, surveillance, immersive teleconferencing and free view-point television are few notable applications of multi-view video. Excessive storage and transmission bandwidth requirements are the major challenges faced by the industry in facilitating multi-view video applications. This paper presents efficient tools for coding of multi-view video based on the state of the art single view video coding standard H.265/HEVC (High Efficiency Video Coding). Our approach employs the LDI (Layered Depth Image) representation technique which is capable of compactly representing 3D scene content. We propose techniques and algorithms for LDI construction, view synthesis, efficient coding of LDI layers and associated auxiliary information. Subjective assessments indicate that our approach offers more than 50% reduction in bitrate compared to HEVC simulcast for the same subjective quality under practical operating bitrates.

GPU based non-overlapping multi-camera vehicle tracking

Vehicle tracking and surveillance is an area which is having a considerable attention in the context of security and safety. The detection and tacking of moving vehicles through multiple cameras is considered as a method of vehicle surveillance. This work addresses a problem of detecting and matching vehicles through multiple cameras. The power of GPUs are used to increase the number of video streams which can be processed using a single computer. In the detection process the Gabor filter is used as a directional filter and the SURF is used by the matcher to uniquely represent the vehicle.