Akashi Satoh

Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates

The first contribution of our paper is that we propose a platform, a design strategy, and evaluation criteria for a fair and consistent hardware evaluation of the second-round SHA-3 candidates. Using a SASEBO-GII field-programmable gate array (FPGA) board as a common platform, combined with well defined hardware and software interfaces, we compare all 256-bit version candidates with respect to area, throughput, latency, power, and energy consumption. Our approach defines a standard testing harness for SHA-3 candidates, including the interface specification for the SHA-3 module on our testing platform. The second contribution is that we provide both FPGA and 90-nm CMOS application-specific integrated circuit (ASIC) synthesis results and thereby are able to compare the results. Our third contribution is that we release the source code of all the candidates and by using a common, fixed, publicly available platform, our claimed results become reproducible and open for a public verification.

Side-channel AttacK User Reference Architecture board SAKURA-G

A new cryptographic standard FPGA board SAKURA-G equipped with a 45-nm Xilinx Spartan-6 was developed to evaluate the security of cryptographic circuits against physical attacks and to measure the hardware performance of encryption algorithms. In addition to its rich array of capabilities, improved power analysis functionality over previous standard boards SASEBO-GII and SASEBO-G is demonstrated thorough CPA (Correlation Power Analysis) on an AES circuit.

Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays

In this study, the properties of physical unclonable functions (PUFs) for 28-nm process field-programmable gate arrays (FPGAs) are examined. A PUF is a circuit that generates device-specific IDs by extracting device variations. Owing to device variation, no two PUFs will generate the same ID even if they have identical structures and are manufactured on the same silicon wafer. However, because the influence of device variation increases as the size of the process node shrinks, it is uncertain whether PUFs can be built using recently developed small-scale process nodes, even though the technology of variation control is constantly advancing. While many PUFs using 40-nm or larger process nodes have been reported, smaller devices have not yet been studied to the authors’ knowledge, and this is the first published journal article on PUFs for 28-nm process FPGAs. In this paper, within-die reproducibility, die-to-die uniqueness, and other properties are evaluated, and the feasibility of PUFs on 28-nm FPGAs is discussed.

Clock glitch generator on SAKURA-G for fault injection attack against a cryptographic circuit

SAKURA-G (Side-channel AttacK User Reference Architecture - G) board equipped with two Spartan-6 FPGAs was developed for physical attack experiments against a cryptographic circuit as a successor to SASEBO-GII. In this work we developed a clock manipulator for SAKURA-G, which generate glitch noises to provoke malfunctions on a cryptographic circuit. By using the DCM (Digital Clock Manager) and PLL (Phase Locked Loop) of the Spartan-6 FPGA, precise control of the glitch injection was achieved. Through fault injection attack experiments against AES (Advanced Encryption Standard) circuit, the advantage of SAKURA-G over SASEBO-GII is demonstrated.

FPGA implementation of authenticated encryption algorithm Minalpher

A new authenticated encryption algorithm Minalpher [1] submitted to CAESAR (Competition for Authenticated Encryption: Security, Applicability, and Robustness) [2] was implemented on various FPGA devices with straightforward and pipelined hardware architectures. Then, its performances in operating speed, hardware size, and power consumption were compared with a current standard algorithm AES-GCM [3] to show the advantages of Minalpher in compact and high-speed hardware implementations.

FPGA implementation of new standard hash function Keccak

High-speed hardware for Keccak, which was selected as a new standard hash function named SHA-3, was developed and its performance was evaluated against SHA-1 and -2 circuits through the use of various FPGA platforms. The results showed that Keccak is suitable for high-speed hardware implementations, but it is getting harder to implement on new FPGA devices, due to the current trends in architecture for state-of-the-art FPGAs. We also clarify the drawbacks of Keccak due to its structure.

High-accuracy and low-cost sensor module for hydroponic culture system

A high accuracy sensor module for hydroponic culture system was developed. The module measures water level, temperature, and nutrient concentration values by using a single device equipped with a low-cost ribbon cable and electrodes. The module has two oscillators and the water level and the concentration value are converted into frequencies of the oscillator signals. After the conversion mechanism and adjustment scheme are explained, the high accuracy of the sensor module is demonstrated.

Side-channel Attack user reference architecture board SAKURA-W for security evaluation of IC card

Side-channel Attack User Reference Architecture board SAKURA-W was developed to evaluate the physical security of IC cards equipped with cryptographic function. SAKURA-W works as a daughter board of SAKURA-G and uses hardware resources of SAKURA-G such as a controller FPGA and a USB interface. In this paper, we describe the basic functionality of SAKURA-W, and show its advantages over SASEBO-W, which is a conventional IC card evaluation board, through side-channel attack experiments using AES software on an 8-bit processor IC card ATMega163.

Comparison of side-channel attack on cryptographic cirucits between old and new technology FPGAs

SASEBO and SAKURA, boards developed for physical security analysis of cryptographic circuits against side-channel attacks, are FPGAs of different generations. The attacks perform statistical analysis on power or electromagnetic waveforms, and enhance leakage signals caused by a secret key. However, the signal becomes weaker along with the advancing miniaturization and high integration of semiconductor process technology. In this paper, power and electro-magnetic attacks against AES (Advanced Encryption Standard) circuits on the FPGA boards are conducted. Then, it is demonstrated that the amplitude of the signal is not dominant, but S/N ration defined as power related to the secret key / power of other circuit activities is important.

GPGPU software implementation of authenticated encryption algorithm Minalpher

Minalpher is an authenticated encryption algorithm submitted to CAESAR (Competition for Authenticated Encryption: Security, Applicability, and Robustness) as a candidate of a new standard algorithm. Performance evaluation of Minalpher in various software and hardware have been made. Especially, the algorithm is suitable for high-speed hardware implementation by utilizing its parallel operating capability. Therefore, we implemented the high-speed Minalpher software on GPGPU (General Purpose Graphic Processing Unit) that provides massive parallel computing. Its performance is compared with Minalpher on CPU and a de-facto standard AES-GCM on GPGPU.