Akhilesh Tyagi

A reduced-area scheme for carry-select adders

The carry-select or conditional-sum adders require carry-chain evaluations for each block for both the values of block-carry-in, 0 and 1. The author introduces a scheme to generate carry bits with block-carry-in 1 from the carries of a block with block-carry-in 0. This scheme is then applied to carry-select and parallel-prefix adders to derive a more area-efficient implementation for both the cases. The proposed carry-select scheme is assessed relative to carry-ripple, classical carry-select, and carry-skip adders. The analytic evaluation is done with respect to the gate-count model for area and gate-delay units for time. >

Preventing IC Piracy Using Reconfigurable Logic Barriers

Hardware metering to prevent IC piracy is a challenging and important problem. The authors propose a combinational locking scheme based on intelligent placement of the barriers throughout the design in which the objective is to maximize the effectiveness of the barriers and to minimize the overhead.

A reconfigurable multifunction computing cache architecture

A considerable portion of a microprocessor chip is dedicated to cache memory. However, not all applications need all the cache storage all the time, especially the computing bandwidth-limited applications. In addition, some applications have large embedded computations with a regular structure. Such applications may be able to use additional computing resources. If the unused portion of the cache could serve these computation needs, the on-chip resources would be utilized more efficiently. This presents an opportunity to explore the reconfiguration of a part of the cache memory for computing. Thus, we propose adaptive balanced computing (ABC)-dynamic resource configuration on demand from application-between memory and computing resources. In this paper, we present a cache architecture to convert a cache into a computing unit for either of the following two structured computations: finite impulse response and discrete/inverse discrete cosine transform. In order to convert a cache memory to a function unit, we include additional logic to embed multibit output lookup tables into the cache structure. The experimental results show that the reconfigurable module improves the execution time of applications with a large number of data elements by a factor as high as 50 and 60.

A reduced area scheme for carry-select adders

For a medium-speed addition application, a carry-skip adder is usually preferred over a carry-select adder, due to its smaller area. A reduced-area carry-select adder scheme in which the second copy of the carry-chain is substituted by an OR gate per bit position is proposed. This alternative implementation for a carry-select adder reduces the relative area advantage of a carry-skip adder to roughly 35%. Replacing the ripple-carry blocks with parallel-prefix blocks results in a select-prefix adder with a slightly better area and time than a parallel-prefix adder.<<ETX>>

Control flow based obfuscation

A software obfuscator is a program O to transform a source program P for protection against malicious reverse engineering. O should be correct (O(P) has same functionality with P), resilient (O(P) is resilient against attacks), and effective (O(P) is not too much slower than P). In this paper we describe the design of an obfuscator which consists of two parts. The first part extracts the control flow information from the program and saves it in another process named Monitor-process. The second part protects Monitor-process converting it into an Aucsmith like self-modifying version. We prove the correctness of the obfuscation scheme. We assess its resilience and efficiency to show that both are This supports the claim that our approach is practical.

A reconfigurable multi-function computing cache architecture

A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially the computing bandwidth limited applications. Instead, such applications may be able to use some additional computing resources. If the unused portion of the cache could serve these computation needs, the on-chip resources would be utilized more efficiently. This presents an opportunity to explore the reconfiguration of a part of the cache memory for computing. In this paper, we present a cache architecture to convert a cache into a computing unit for either of the following two structured computations, FIR and DCT/IDCT. In order to convert a cache memory to a function unit, we include additional logic to embed multi-bit output LUTs into the cache structure. Therefore, the cache can perform computations when it is reconfigured as a function unit. The experimental results show that the reconfigurable module improves the execution time of applications with a large number of data elements by a large factor (as high as 50 and 60). In addition, the area overhead of the reconfigurable cache module for FIR and DCT/IDCT is less than the core area of those functions. Our simulations indicate that a reconfigurable cache does not take a significant delay penalty compared with a dedicated cache memory. The concept of reconfigurable cache modules can be applied at Level-2 caches instead of Level-1 caches to provide an active-Level-2 cache similar to active memories.

HORNS: A homomorphic encryption scheme for Cloud Computing using Residue Number System

In this paper, we propose a homomorphic encryption scheme using Residue Number System (RNS). In this scheme, a secret is split into multiple shares on which computations can be performed independently. Security is enhanced by not allowing the independent clouds to collude. Efficiency is achieved through the use of smaller shares.

Efficient parallel algorithms for optical computing with the discrete Fourier transform (DFT) primitive

Optical-computing technology offers new challenges to algorithm designers since it can perform an n-point discrete Fourier transform (DFT) computation in only unit time. Note that the DFT is a nontrivial computation in the parallel random-access machine model, a model of computing commonly used by parallel-algorithm designers. We develop two new models, the DFT-VLSIO (very-large-scale integrated optics) and the DFT-circuit, to capture this characteristic of optical computing. We also provide two paradigms for developing parallel algorithms in these models. Efficient parallel algorithms for many problems, including polynomial and matrix computations, sorting, and string matching, are presented. The sorting and string-matching algorithms are particularly noteworthy. Almost all these algorithms are within a polylog factor of the optical-computing (VLSIO) lower bounds derived by Barakat and Reif [Appl. Opt. 26, 1015 (1987) and by Tyagi and Reif [Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing (Institute of Electrical and Electronics Engineers, New York, 1990) p. 14].

Low power FSM design using Huffman-style encoding

This paper presents a novel approach to synthesize low power FSMs using non-uniform code length. Switching activity is reduced by decreasing the expected number of state bits switched less than [log |S|] The state set S of the FSM is decomposed into two sets based on the limit state probabilities. The state set with very high probability is encoded with less than [log|S|] bits. The other state set, being less probable, is encoded using more than [log|S|] bits. To the best of our knowledge, this is the first time two code lengths ore used for one state machine. This encoding is realized by using flip-flops with gated clock. The logic generating the enable signal of the clock uses only a single minterm. The state sets can be encoded using any uniform-length encoding algorithm with objectives of low power and low area. The experiments show an average of 13% and 18% reduction in power for two encoding algorithms respectively.

Re-encoding for low power state assignment of FSMs

The state assignment problem for nite state machines has been explored extensively by the logic synthesis and asynchronous design communities. In this paper, we introduce the concepts of base switching and relative switching. We present a fast intelligent exchange based re-encoding algorithm for reducing average switching. The reasons for the speed of this iterative algorithm are given along with an analysis of its time complexity. Experimental results on sequential circuits from the MCNC benchmark set show that switching activity can be reduced by 75%(max) and 35-47%(average). Power savings of 50%(max) and 10-18%(average) were obtained with negligible increase in area. Based on the experimental results we draw conclusions about the best choice of a starting point for the re-encoding algorithm.