Akihiro Tamba

CMOS-compatible lateral bipolar transistor for BiCMOS technology. I. Modeling

A CMOS-compatible lateral bipolar transistor having neither an epitaxial layer nor n/sup +/-buried layers is proposed. The simulation indicates that the BiCMOS gate delay time shows a weak dependence on the metallurgical base width W/sub B/, (and hence on f/sub Tmax/, since f/sub T/ varies as 1/W/sub B//sup 2/) and strong dependence on the effective base width W/sub B(eff)/, where W/sub B(eff)/ nearly equals the distance between the emitter and the n/sup +/ collector, d/sub E-C/. This is because bipolar transistors in BiCMOS circuits are operated in high-level injection during the switching transient. Therefore, it is possible to build a high-speed BiCMOS gate using lateral bipolar devices with short d/sub E-C/. The transistor has a structure similar to that of an n-channel MOSFET. The emitter and collector are formed simultaneously and self-aligned to a polysilicon base electron like the source and drain in a MOSFET. >

A novel CMOS-compatible lateral bipolar transistor for high-speed BiCMOS LSI

A CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs is proposed, and its high-speed characteristics are demonstrated. The proposed lateral bipolar transistor has a structure analogous to NMOS transistors, which use a source and drain self-aligned structure to form an emitter and collector. The obtained values of h/sub FE/, BV/sub CEO/, R/sub CS/, f/sub TMAX/, and r/sub bb/, are 20, 7 V, 50 Omega , 6.3 GHz, and 450 Omega , respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 ns and 0.53 ns when load capacitances are 1 pF and 2 pF, respectively. These values are equal to those of conventional poly-Si emitter bipolar transistors.<<ETX>>