Akiko Narita

Execution time measurement of a vector operation on LSC-Based DSP

In this paper, we describe the performance measurement of a new DSP processor based on the dataflow execution model. Our proposed DSP processor is in contrast to most recent DSP processors based on von Neumann paradigm. We call our DSP as LSC-Based DSP because it is a specialized Loop Structured Computer (LSC) which is a parallel dataflow computer developed in our laboratory. In our measurement, we choose a vector operation as a benchmark algorithm because a vector operation is involved in most DSP algorithms and inherently equivalent to a program in a dataflow computer. LSC-Based DSP is designed in hardware description language and implemented on a field programmable gate array (FPGA). We measure the execution time of a vector operation on LSC-Based DSP with varying some design parameters. The measurement result shows the ability for parallel execution of LSC-Based DSP with several dataflow processing elements. In practice, the execution time of LSC-Based DSP with seven processing elements is approximately five times shorter than that with one processing element.

Autonomous Decision of Function of the Redundant Traffic Reduction Node Using a New IP Option

In recent computer networks, the same data are often transferred repeatedly. We have developed network nodes with packet caches in order to reduce such redundant traffic in TCP/IP network. We call the node TR node. In our previous researches, we had to set up locating information of the TR nodes statically for decision of their function. Additionally, the configuration with multiple encoding TR nodes was unacceptable because of cache competition. In this study, we provided information of location and status for TR node control using a new IP option. We enabled the TR node to decide its function dynamically and avoid cache competition autonomously with the information.

Evaluation of the Redundant Traffic Reduction Node Using the Packet Cache Coping with Different Byte Offsets among Streams

In recent computer networks, amount of redundant traffic by services including video delivery is increasing. Our research group improved performance of network node that reduces the redundant traffic with the packet cache. When differences of byte offsets among redundant streams increase, the node requires large cache. We implemented the new function in the node that restrains replacement of the data in the cache when the differences are large. We successfully decreased frequency of removing data that would be referred soon. Therefore, the node reduced the traffic efficiently with smaller size cache.

Expansion of operations in a multicore dataflow DSP

Nowadays, there are numerous multicore processors for parallel computing. The potential for parallelism is inherently provided by the dataflow execution model, which is a natural fit for exploiting the parallelism inherent in programs, especially digital signal processing applications. In our laboratory, we have developed a ring interconnected multicore dataflow DSP called LSC-Based DSP. In this work we supplement a subtraction operation to LSC-Based DSP with the function of duplicating operand data in order to provide a higher degree of programmability. We implement the new our DSP on an FPGA development board, and verify the functionality of the subtraction instruction by executing several test programs on our new DSP.

CFBLT: A Closed Feed Back Loop Type Queuing System; Modeling and Analysis

This paper presents an innovative approach to solve probability distributions of a close feed back loop type queuing system with general service time distribution. This model is applied to a multi-processors system where some of its nodes are performed a repair procedure during a node’s malfunction condition. Our model is appropriate for a multiprocessor system that employs a common bus or for a multi-node system in computer network. A meticulous analysis of the system’s model has been conducted and numerical results have been obtained to scrutinize the proposed model.

Comprehensive Evaluation of Packet Flow Control Methods for a Ring Nework of Processors on Chip

A Current design of a system-on-chip (SoC) technology is constructing under increasing demand for high performance, small size and energy-efficient design. To fulfill these demands, it is required to consider a suitable design for on chip interconnection network. In this paper, we design a prototype of communications unit (CU) for a network-on-chip (NoC) architecture based on ring processors interconnection whose structure is simple to provide a SoC model with small size, low-cost and low energy consumption solutions for designing SoC system. Three types of packet flow control methods, such as, store-and-forward (SF), virtual cut-through (VCT) and wormhole routing (WH) have been implemented and compared in view of designing a hardware-efficient SoC architecture. Furthermore, computer based simulations with a clock cycle level of a CPU in the CU were preformed and transmission latency, throughput, and capability for load balancing were analyzed and compared. From the results that have been obtained show that VCT gives better performances, while SF and WH are more economical in memory consumption for short and long packet length, respectively.