Akintunde Ibitayo Akinwande

Tunable threshold voltage and flatband voltage in pentacene field effect transistors

Charged interface states are introduced by UV-ozone treatment of a polymer gate dielectric, parylene, prior to deposition of the organic semiconductor, pentacene, thereby modifying the organic field effect transistor (OFET) operation from enhancement to depletion mode. Quasistatic capacitance-voltage measurements and the corresponding current-voltage characteristics show that the threshold voltage VT and flatband voltage VFB can be shifted by over +50V, depending on the ozone exposure time. This work demonstrates that careful control of the semiconductor-insulator interface state densities is essential to VT and VFB control and the fabrication of reliable OFET integrated circuits.

Low-voltage organic transistors and depletion-load inverters with high-K pyrochlore BZN gate dielectric on polymer substrate

Pentacene organic thin-film transistors (OTFTs) have demonstrated the highest performance among TFTs with an organic semiconductor channel. High operating voltages (20-100 V), stemming from poor capacitive coupling between gate electrode and channel, are a major limitation, particularly for portable battery-powered device applications. OTFTs fabricated on flexible polymer substrates, often characterized by rough surfaces, benefit from the use of high-K dielectrics given the ability to accommodate thicker films which ensure the pinhole-free and good coverage without need to increase operating voltage. As we demonstrate, pyrochlore structured thin films can provide the requisite high dielectric constant coupled with excellent leakage current characteristics, while remaining compatible with the processing requirements of flexible OTFTs. The introduction of an extremely thin parylene film between the BZN dielectric and the pentacene semiconductor markedly shifts the threshold voltage, making it possible to fabricate both enhancement (E) and depletion (D) TFTs. We report the successful fabrication of low-voltage (<2 V) organic transistors and depletion-load inverter using a 200-nm-thick pyrochlore gate dielectric, Bi/sub 1.5/Zn/sub 1.0/Nb/sub 1.5/O/sub 7/ (BZN), prepared by a room temperature process. The inverters with depletion load were successfully operated under 5 V with excellent noise margin.

A Micro-Fabricated Linear Array of Electrospray Emitters for Thruster Applications

This paper reports the design, fabrication, and experimental characterization of an internally fed linear array of electrospray emitters intended for space propulsion applications. The engine uses doped formamide as propellant and operates in the single-Taylor-cone droplet emission regime. The engine implements the concept of hydraulic and electrodynamic flow rate matching to achieve electrical control. The engine uses a set of meso-scaled silicon deflection springs to assemble the hydraulics to the electrodes, allowing to decouple the corresponding process flows. The micro-fabrication of the engine is described and novel technologies that were developed are reported. Experimental results that demonstrate cumulative uniform and steady operation are provided. Current-flowrate characteristics of the engine are in agreement with a reduced-order model. Experimental data demonstrating the low divergence of electrospray emitter arrays operated in the single Taylor Cone is in qualitative agreement with a reduced-order mode that assumes the absence of a thermalized tail in the plume

Silicon field emission arrays with atomically sharp tips: turn-on voltage and the effect of tip radius distribution

We report 1 nm tip radius, 1 /spl mu/m gate-aperture silicon field emission arrays (FEAs) with turn-on voltage as low as 14 V. The low turn-on voltage is attributed to the small emitter tip radius, which was achieved by isotropic etching of silicon and low-temperature oxidation sharpening. Optimization of the oxidation sharpening process reduced the tip radius to less than 1 nm and was confirmed by transmission electron microscopy (TEM). The tip radius has a log-normal distribution with a peak at 0.75 nm, an expected value of 1.8 nm, and shape parameter of 0.74 nm. Current-voltage (I-V) characteristics of the field emission devices are in agreement with Fowler-Nordheim (FN) theory. The extracted tip radius using two-dimensional (2-D) numerical simulation showed good agreement with the TEM measurements.

Engineering density of semiconductor-dielectric interface states to modulate threshold voltage in OFETs

Threshold-voltage control is critical to the further development of pentacene organic field-effect transistors (OFETs). In this paper, we demonstrate that the threshold voltage can be tuned through chemical treatment of the gate dielectric layer. We show that oxygen plasma treatment of an organic polymer gate dielectric, parylene, introduces traps at the semiconductor-dielectric interface that strongly affect the OFET performance. Atomic force microscopy, optical microscopy using crossed-polarizers, and current-voltage and capacitance-voltage characterization were performed on treated and untreated devices. A model is presented to account for the effects of trap-introduced charges, both 1) fixed charges (2.0/spl times/10/sup -6/ C/cm/sup 2/) that shift the threshold voltage from -17 to +116 V and 2) mobile charges (1.1/spl times/10/sup -6/ C/cm/sup 2/) that increase the parasitic bulk conductivity. This technique offers a potential method of tuning threshold voltage at the process level.

A lithographic process for integrated organic field-effect transistors

This paper reports a photolithographic process for fabricating organic field-effect transistors which provides two layers of metal with arbitrary via placement, and optionally allows for subtractive lithographic patterning of the transistor active layer. The demonstrated pentacene transistors have a field-effect mobility of 0.1/spl plusmn/0.05 cm/sup 2//(V/spl middot/s). Parylene-C is used both as the gate dielectric and an encapsulation layer which allows for subtractive lithographic patterning. Also demonstrated is a PMOS inverter without level shifting circuitry and level-restoring V/sub High/ and V/sub Low/. This work demonstrates a high definition, multilayer, integrated photolithographic process which creates organic field effect transistors suitable for use in integrated circuit applications such as a display backplanes.

Mixed-Signal Organic Integrated Circuits in a Fully Photolithographic Dual Threshold Voltage Technology

Analog & digital circuits implemented in a dual threshold voltage (VT) p-channel organic technology are presented. The dual VT organic technology is compatible with large-area and mechanically flexible substrates due to its low processing temperature (≤ 95°C) and scalable patterning techniques. We demonstrate the first analog & digital organic integrated circuits produced by a dual-gate metal process. The analog circuits are powered by a 5-V supply and include a differential amplifier and a two-stage uncompensated operational amplifier (op-amp). A dynamic comparator is measured to have an input offset voltage of 200 mV and latching time of 119 ms. Both the comparator and the op-amp dissipate 5 nW or less. Area-minimized digital logic is presented. Inverters powered by a 3-V supply were measured to have positive noise margins and consumed picowatts of power. An 11-stage ring oscillator, also powered by a 3-V supply, swings near rail to rail at 1.7 Hz. These results demonstrate dual threshold voltage process feasibility for large-area flexible mixed-signal organic integrated circuits.

CNT-Based MEMS/NEMS Gas Ionizers for Portable Mass Spectrometry Applications

We report the fabrication and experimental characterization of a carbon nanotube (CNT)-based MEMS/NEMS electron impact gas ionizer with an integrated extractor gate for portable mass spectrometry. The ionizer achieves low-voltage ionization using sparse forests of plasma-enhanced chemical-vapor-deposited CNTs as field emitters and a proximal extractor grid with apertures aligned to the CNT forests to facilitate electron transmission. The extractor gate is integrated to the ionizer using a high-voltage MEMS packaging technology based on Si springs defined by deep reactive ion etching. The ionizer also includes a high-aspect-ratio silicon structure (¿foam) that facilitates sparse CNT growth and also enables uniform current emission. The devices were tested as field emitters in high vacuum (10-8 torr) and as electron impact ionizers using argon at pressures of up to 21 mtorr. The experimental data show that the MEMS extractor gate transmits up to 66% of the emitted current and that the ionizers are able to produce up to 0.139 mA of ion current with up to 19% ionization efficiency while consuming 0.39 W.

Leading, Following or Cooked Goose? Innovation Successes and Failures in Taiwan's Electronics Industry

The reasons behind the innovation successes and failures in the Taiwanese electronics industry have been widely discussed. This paper makes its contribution to the debate by comparing the innovation outcomes for three products: complimentary metal oxide silicon (CMOS) logic, dynamic random access memory (DRAM) and active matrix liquid crystal displays (AMLCDs). Four success factors are identified to characterize products where the Taiwanese pursue innovation: granularity of production; absence of need for large amounts of patient capital; volume production; and manufacturing-based production. In turn, this paper argues that products exhibiting these characteristics succeed because such characteristics draw upon the institutional and historical strengths of the Taiwanese economy. The paper broadens the inquiry to assess what lessons the Taiwanese innovation successes have for developing countries. It is argued that the new lesson Taiwan has to offer is that countries can become innovators by concentrating their human and financial capital through granularization of production.increasingly relevant. It is argued here that social networks sustain interpersonal routines, which not only transgress organizational boundaries but on occasion also incubate new organizations in order to ensure their continued existence. This paper presents an overview of the routine concept and an argument for applying it in a network embeddedness context. Two case studies are presented, covering examples from the Danish dairy and the Danish machinery industry.

Dual Threshold Voltage Organic Thin-Film Transistor Technology

A fully photolithographic dual threshold voltage (VT) organic thin-film transistor (OTFT) process suitable for flexible large-area integrated circuits is presented. The nearroom-temperature (<; 95 °C) process produces integrated dual VT pentacene-based p-channel transistors. The two VT s are enabled by using two gate metals of low (aluminum) and high (platinum) work function. The Al and Pt gate OTFTs exhibit nominally identical current-voltage transfer curves shifted by an amount ΔVT. The availability of a high-VT device enables area-efficient zero-Vos high-output-resistance current sources, enabling high-gain inverters. We present positive noise margin inverters and rail-to-rail ring oscillators powered by a 3-V supply-one of the lowest supply voltages reported for OTFT circuits. These results show that integrating nand p-channel organic devices is not mandatory to achieve functional area-efficient low-power organic integrated circuits.