Akio Harasawa
NEC
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Publication
Featured researches published by Akio Harasawa.
custom integrated circuits conference | 1997
Akio Harasawa; Teruo Kaganoi; Toshiyuki Kanoh; Hideki Nishizaki; Masanobu Suzuki; Hitoshi Tomizawa; Takeshi Shindou
An application specific integrated processor designed for ATM cell processing applications is described in this paper. A new dedicated architecture consisting of a custom-made CPU core, a pipeline input cell buffer and a content addressable memory (CAM) is employed to realize both high performance data processing and functional re-configurability. The chip has been implemented on 0.5 /spl mu/m CMOS. It consumes 2400 mW power under 3.3 V supply at 52 MHz clock frequency for a 155 Mbps high speed cell data stream. Programs for several different applications have been developed and are running on this chip. As a result of evaluation, each application program satisfies a required performance.
Archive | 2001
Akio Harasawa
Archive | 2001
Teruo Kaganoi; Toshiyuki Kanoh; Akio Harasawa
Archive | 2001
Akio Harasawa; Toshiyuki Kanoh
Archive | 1997
Akio Harasawa; Teruo Kaganoi
Archive | 2000
Akio Harasawa; Teruo Kaganoi
Archive | 1997
Teruo Kaganoi; Akio Harasawa
Archive | 2001
Akio Harasawa; Toshiyuki Kanoh
Archive | 1996
Akio Harasawa
Proceedings of the IEICE General Conference | 2000
Teruo Kaganoi; Eriko Okuno; Akio Harasawa
