Akira Kanemasa

24- and 120-Channel Transmultiplexers Built with New Digital Signal Processing LSI's

Two new digital transmultiplexers intended for commercial use have been developed. One transmultiplexer performs a bilateral conversion between two 12-channel FDM group signals and a 24-channel PCM carrier signal. The other mutually connects two 60Channel FDM supergroup signals and five 24-channel or four 30channel PCM signals. Both exploit a block processing digital SSBFDM multiplex/demultiplex scheme employing a cascade of an FFT processor and a set of complex coefficient digital filters. They have been built using newly developed high-level DSP LSI chips. Algorithmic considerations, developed LSI architecture, and equipment configuration are described as well as digital processor design details and measured performance.

An LSI chip set for DSP hardware implementation

This paper describes a new LSI chip set developed to provide a simple and cost-effective means for DSP hardware implementation. This chip set, consisting of two NMOS LSIs, contains enough logic and memory to perform such high level DSP functions as biquad filters and FFT butterflies at a high throughput rate, without any other external logic devices. It employs serial arithmetic and operates at a clock rate up to more than 5 MHz. Throughput rate can be traded-off with processing accuracy. Architecture is designed to pursue self-sufficient applicability to high level DSP functions, while retaining generality in application.

An ISDN echo-cancelling transceiver chip set for 2B1Q coded U-interface

A 5-V CMOS chip set used for an integrated services digital network (ISDN) U-interface transceiver is described which accomplishes 2B+D channel (144-kb/s) transmission using a 2B1Q line code based on echo cancellation over existing two-wire subscriber loops. The three-chip set consists of an analog front end (AFE), an echo canceler (ECD) and a receiver (RCV). The last two are digital signal processors. The AFE has been fabricated in double-polysilicon double-metal 1.6 mu m CMOS technology. The chip size is 7.5 mm*6.5 mm. The EC and RCV have been fabricated in double-metal 1.2- mu m CMOS technology using a standard-cell design. The chip sizes are 8.2 mm*8.2 mm and 8.5 mm*8.1 mm, respectively. Total power consumption of the chip set is 580 mW with a single 5-V supply.<<ETX>>

Design techniques and performance of an LSI-based 2B1Q transceiver

Examines a 2B1Q transceiver system which was selected as the standard for an ISDN (integrated services digital network) loop transmission systems in the US. An LSI-based 2B1Q transceiver consisting of three LSI chips has been developed. Echo tail suppression, receiver design to configure stable decision feedback equalizer (DFE) operation and to improve NEXT performance, and the accurate analog front end circuit are discussed. Experimental results show that satisfactory performance is obtained.<<ETX>>

STM-ATM migration plan with bridge functions

The implementation of the asynchronous transfer mode (ATM) network, as one of the vehicles for B-ISDN services, has been the subject of many enthusiastic studies. ATM networks will gradually expand to meet societys needs for B-ISDN. Since connections with existing STM networks will be required in this process of expansion, it is necessary to analyze bridge functions with them. It is also imperative that the main parts of services provided through existing STM networks such as plain old telephone services (POTS) and N-ISDN basic access services (2B+D) be efficiently integrated into an ATM network. The paper classifies and compares bridge functions with STM networks while clarifying an ATM network introduction scenario. The paper then studies the function that is considered to be most important, ATM cell assembly and disassembly (CLAD) for POTS and 2B+D service signals.<<ETX>>

An adaptive filter convergence method for echo cancellation and decision feedback equalization

This paper proposes a new convergence method for adaptive digital filters applied to echo cancellation and decision feedback equalization. The proposed method, using Disturbing Signal Canceler (DSC), saves adaptive filters from falling into a deadlock. DSC takes advantage of a line code property, wherein the number of symbol waveforms is limited and each waveform has both polarities. Since DSC is realized simply with an adder and a delay element, it is suitable for LSI implementation. Theoretical analyses were carried out to show the convergence characteristics and the convergence condition. Computer simulations prove that both an echo canceler and a decision feedback equalizer based on the proposed method, employing DSC, possess satisfactory performance.