Akira Yamawaki

Coherence maintenances to realize an efficient parallel processing for a cache memory with synchronization on a chip-multiprocessor

A chip-multiprocessor is one of the promising architectures that can overcome the ILP limitation, high power consumption and high heating that current processors face. On a shared memory multiprocessor, a performance improvement relies on an efficient communication and synchronization method via shared variables. The TSVM cache combines communication and synchronization with the coherence maintenance on a chip-multiprocessor. That is, the communication and synchronization via shared variables are realized by one coherence transaction through a high-speed on chip inter-connection. The TSVM cache provides several instructions that each instruction has the individual coherence maintenance scheme. The combinations of these instructions can realize the producer-consumers synchronization, mutual exclusion and barrier synchronization with communication easily and systematically. This paper describes how those instructions construct three primitives and shows effect of these primitives using a clock cycle-accurate simulator written in VHDL. The result shows that the TSVM cache can improve a performance of 9.8 times compared with a traditional cache memory, and improve a performance of 2 times compared with a conventional cache memory with synchronization mechanism.

Underwater optical image dehazing using guided trigonometric bilateral filtering

This paper describes a novel method to enhance underwater optical images by dehazing. Scattering and color change are two major problems of distortion for underwater imaging. Scattering is caused by large suspended particles, like fog or turbid water which contains abundant particles, plankton etc. Color change corresponds to the varying degrees of attenuation encountered by light traveling in the water with different wavelengths, rendering ambient underwater environments dominated by a bluish tone. Our key contribution is to propose a fast image and video dehazing algorithm, to compensate the attenuation discrepancy along the propagation path, and to take the influence of the possible presence of an artificial lighting source into consideration. The enhanced images are characterized by reduced noised level, better exposedness of the dark regions, improved global contrast while the finest details and edges are enhance significantly. In addition, our enhancement method is comparable to higher quality than the state-of-the-art methods.

Curvelet Approach for Deep-sea Sonar Image Denoising, Contrast Enhancement and Fusion

Side-scan sonar acquires high quality imagery of the seafloor with very high spatial resolution but poor locational accuracy. However, multi-beam sonar obtains high precision position and underwater depth in seafloor points. In order to fully utilize all information of these two types of sonars, it is necessary to fuse the two kinds of sonar data. This paper gives curvelet transform for enhancing the signals or details in different scales separately. It also proposes a new intensity sonar image fusion method, which is based on curvelet transform. Considering the sonar image forming principle, for the low frequency curvelet coefficients, we use the maximum local energy method to calculate the energy of two sonar images. For the high frequency curvelet coefficients, we take absolute maximum method as a measurement. The main attribute of this paper is: Firstly, the multi-resolution analysis method is well adapted the cured-singularities and point-singularities. It is useful for sonar intensity image enhancement. Secondly, maximum local energy is well performing the intensity sonar images, which can achieve perfect fusion result. The experimental results show that the method can be used in the flat seafloor or the isotropic seabed. Compared with wavelet transform method, this method can get better performance.

An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip

FPGA based multiprocessor SoC (MPSoC) is an on-chip multiprocessor with fully programmable feature which can reduce development cost and achieve performance requirement. In order to provide an MPSoC with the low-overhead communication and synchronization methods, this paper attempts to introduce the TSVM (tagged shared variable memory) cache to a snooping cache on the MPSoC. The TSVM cache can improve a performance by combining communication and synchronization with the coherence maintenance. Using an FPGA, we evaluate how extending a conventional snooping cache affects circuitries and clock speed. As a result, the growth of hardware amount and the degradation of clock speed are only 5% and 2% respectively. It is also confirmed that the TSVM cache improves significantly performance and energy efficiency by stalling in synchronization.

A sensor node architecture with zero standby power on wireless sensor network

The wireless sensor network (WSN) is a promising technology to improve the social life cooperating with the robotic technologies like nursing robots, disaster rescue robots, industrial robots, and so on. For such WSN, we propose an architecture of the sensor node with zero standby power consumption. This is accomplished by combining a power transistor cutting the ground line, an electromotive from a sensor for just turning on the power transistor and a conventional battery. The preliminary experiments demonstrate that our proposal can actually activate the sensor node, which stays at the sleep mode with zero power consumption, with a short-time electromotive force generated by the piezoelectric sensor. It is also confirmed that the sensor node activated can establish the wireless communication correctly.

Tagged communication and synchronization memory for multiprocessor‐on‐a‐chip

Multiprocessor-on-a-chip is becoming possible due to progress in semiconductor technologies. In the multiprocessor, the threaded parallel processing requires decreasing the overhead of interthread communication and synchronization. We propose the tagged communication and synchronization memory with the access counter using CAM (TCSM) which supports a high-speed mechanism for the mutual exclusion, the condition synchronization, the barrier synchronization, and the multicasting between the threads. TCSM allocates its entries dynamically and ensures the producer–consumer synchronization by valid/invalid state in the access count. The execution environment of the threads is protected because the tag of TCSM is used for identifying both the task which threads belong to and the storage used by threads. The MTA/TCSM multichip multiprocessor system has been developed to evaluate the multiprocessor-on-a-chip including TCSM. As a result of the evaluation on MTA/TCSM, the overhead of interthread synchronization and communication using TCSM is lower than using the conventional shared memory.

Organization of shared memory with synchronization for multiprocessor-on-a-chip

The TSVM is a logical structured memory with a synchronization to improve a performance in a multi-threaded parallel processing. The physical TSVM is realized by the TSVM cache (TC) and a conventional memory in a Multiprocessor-on-a-chip (MOC) system. The L1 cache in a CPU consists of the TC, the General variable cache (GVC) and the instruction cache. The IYA (IY architecture) that is a new architecture divides a conventional data cache into the TC and GVC. The TC caches the shared variables with a synchronization, and the GVC caches other general variables. Regardless of a CPU core, a MOC with the IYA can utilize parallelisms from the instruction level and the statement level to the thread level systematically. To estimate the effect of the TC, preliminary experiments are performed on the multi-chip multiprocessor including the stand-alone TSVM. The result shows that the TSVM cache improves the performance.

Multimodal Medical Image Fusion in Extended Contourlet Transform Domain

As a novel of multi-resolution analysis tool, the modified sharp frequency localized contourlet transforms (MSFLCT) provides flexible multiresolution, anisotropy, and directional expansion for medical images. In this paper, we proposed a new fusion rule for multimodal medical images based on MSFLCT. The multimodal medical images are decomposed by MSFLCT. For the high-pass subband, the weighted sum modified laplacian (WSML) method is used for choose the high frequency coefficients. For the lowpass subband, the maximum local energy (MLE) method is combined with “region” idea for low frequency coefficient selection. The final fusion image is obtained by applying inverse MSFLCT to fused lowpass and highpass subbands. Abundant experiments have been made on groups of multimodality datasets, both human visual and quantitative analysis show that the new strategy for attaining image fusion with satisfactory performance.

An efficient hardware architecture from c program with memory access to hardware

To improve the performance and power-consumption of the system-on-chip (SoC), the software processes are often converted to the hardware. However, to extract the performance of the hardware as much as possible, the memory access must be improved. In addition, the development period of the hardware has to be reduced because the life-cycle of SoC is commonly short. This paper proposes a design-level hardware architecture (semi-programmable hardware: SPHW) which is inserted onto the pass from C to hardware. On the SPHW, the memory accesses and buffers are realized by the software programming and parameters respectively. By using the SPHW you can easily develop the data processing hardware containing the efficient memory access controller at C-level abstraction. Compared with the conventional cases, the SPHW can reduce the development time significantly. The experimental result also shows that you can employ the SPHW as the final product if the memory access latency is hidden enough.

An FPGA implementation of a DWT with 5/3 filter using semi-programmable hardware

The discrete wavelet transform with 5/3 filter of the JPEG2000 shows different memory access patterns according to the levels of decomposition. To make computation faster by hardware implementation, hiding memory access latency is important to improve a performance. The semi-programmable hardware (SPWH) as an intermediate hardware provides an efficient design method of a hardware with data prefetching to hide the memory access latency across the different memory access patterns. This paper describes the SPHW and demonstrates a mapping method for the DWT. The experimental result shows that the SPHW can significantly reduce a design burden and achieve a good performance.