Alaa R. Al-Taee

New 2-D Eye-Opening Monitor for Gb/s Serial Links

This paper presents a new 2-D on-chip eye-opening monitor (EOM) for Gb/s serial links. A comprehensive review of the state-of-the-art of on-chip EOMs is provided and their pros and cons are investigated. A new hexagon 2-D EOM that outperforms the widely used rectangular 2-D EOMs is introduced and the implementation details are presented. The effectiveness of the proposed EOM is evaluated by embedding it in a serial link implemented in an IBM 130 nm 1.2 V CMOS technology. For the purpose of comparison, a rectangular 2-D EOM is also included in the same data link. The data link with a variable channel length and attenuation is analyzed using Spectre from Cadence Design Systems with BSIM four device models. Simulation results of the data link demonstrate that the proposed EOM outperforms the rectangular EOM by providing a tightened control of data jitter at the edge of data eyes and by eliminating unnecessary errors flagged by the rectangular EOM.

Minimum jitter adaptive decision feedback equalizer for 4PAM serial links

This paper presents a minimum jitter-based adaptive decision feedback equalizer (DFE) for 4PAM serial links. For each signal level, a dedicated sign-sign least-mean-square (SS-LMS) algorithm is employed to adjust corresponding DFE tap coefficient as per data rate and the characteristics of channels. The proposed adaptive DFE is embedded in a 2 Gbps serial link over a 12-inch FR4 channel implemented in an IBM 130 nm 1.2V CMOS technology. The link is analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results demonstrate that the proposed adaptive DFE is capable of opening completely closed data eyes.

A new adaptive Decision Feedback Equalizer using hexagon eye-opening monitor for multi Gbps data links

This paper presents an adaptive Decision-Feedback Equalizer ADFE utilizing a proposed hexagon eye-opening monitor for multi Gbps serial links. The adaptation process of proposed ADFE depends on the error signals which are delivered from error detection unit EDU. The EDU employs a hexagon eye-opening monitor H-EOM to detect the violations of the received data signals after the comparison with three threshold voltage levels at two sampling points. The extracted error signals are then conveyed to the input of an adaptive engine. The adaptive engine updates the feedback tap coefficients of the DFE automatically based on these error signals. The examination of the comparison of the proposed DFE architect with the adaptive DFE architect employing a rectangular eye-opening monitor R-EOM shows that the proposed architect obtained better performance for providing convergence time and voltage, and identifying jitter violations. The effectiveness of the proposed architect is validated using the simulation results of a serial link designed in an IBM 130 nm 1.2V CMOS technology.

A new CDMA transmitter for high-speed serial links

Conventional CDMA serial links suffer from the drawback that the number of transmitters is limited to only two in practical implementations due to the reduced voltage spacing between adjacent logic states of the transmitted data. In this paper, we propose a new CDMA serial link architect that allows an arbitrary number of transmitters to transmit data over the same channel simultaneously while keeping the voltage spacing between adjacent logic states of the transmitted data to be the same as that of 4-PAM serial links. The effectiveness of the proposed architect is validated using the simulation results of a serial link with four transmitters designed in an IBM 130 nm 1.2V CMOS technology.

A new simple RC modeling for on-chip interconnects with its applications to buffer insertion

A new improved RC modeling for on-chip interconnects derived from pi-configuration of AWE-Based RLC model is presented. A platform utilized to generate all-possible T- and pi configurations of RC, RLC and RLCG models using GAM, TPN, and AWE methods is proposed. 18 different RC, RLC, and RLCG models are generated based on this platform. The pi-configuration of AWE-RLC model provides the best performance. This model is mapped into an improved RC model to preserve the accuracy of the RLC model while keeping the simplicity of the RC model. As compared with conventional RC model, the simulation results of interconnects delay with buffer insertion show that the proposed RC model improves the delay by 20.5%, reduces the number of required buffers by 24%, and the buffer sizes by 32%.

Two-dimensional eye-opening monitor for serial links

A new hexagon two-dimensional on-chip eye-opening monitor that outperforms the widely used rectangular two-dimensional eye-opening monitor is introduced and its design constraints are derived. The effectiveness of the proposed eye-opening monitor is evaluated by embedding it in a serial link implemented in an IBM 130 nm 1.2V CMOS technology. Simulation results of the data link demonstrate that the proposed eye-opening monitor outperforms the rectangular eye-opening monitor by providing a tightened control of data jitter at the edge of data eyes and by eliminating unnecessary errors flagged by the rectangular eye-opening monitor.