Alaaeldin Amin

High-Radix Multiplier-Dividers: Theory, Design, and Hardware

This paper describes the theory and design of digital high-radix multiplier-dividers (Patent Pending). The theory of high-radix division is extended to high-radix multiplier-dividers that can perform fused multiplication and division operations using a single recurrence relation. With the fused implementation of multiplication and division, the two operations can be executed using a single instruction, implying only a single rounding operation. The recurrence relation is described, the quotient digit selection function derived, and important design parameters together with their optimal values and relations are defined. Efficient design procedure and implementation hardware are described and important system parameter values for various radix systems computed. Compared to pure dividers, the multiplier-divider requires a slightly more complex data path and quotient digit selection function.

Efficient O(/spl radic/n) BIST algorithms for DDNPS faults in dual port memories

The testability problem of dual port memories is investigated. Architectural modifications which enhance testability with minimal overhead on both silicon area and device performance are described. New fault models for both the memory array and the address decoders are proposed and efficient O(/spl radic/n) test algorithms are presented. The new fault models account for the simultaneous dual access property of the device. In addition to the classical static neighborhood pattern sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, Duplex Dynamic Neighborhood Pattern Sensitive faults (DDNPSF).

New fault models and efficient BIST algorithms for dual-port memories

The testability problem of dual-port memories is investigated. A functional model is defined, and architectural modifications to enhance the testability of such chips are described. These modifications allow multiple access of memory cells for increased test speed with minimal overhead on both silicon area and device performance. New fault models are proposed, and efficient O(/spl radic/n) test algorithms are described for both the memory array and the address decoders. The new fault models account for the simultaneous dual-access property of the device. In addition to the classical static neighborhood pattern-sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, duplex dynamic neighborhood pattern-sensitive faults (DDNPSF).

High performance elliptic curve point operations with pipelined GF(2 m ) field multiplier

This paper studies the effect of high performance pipelined GF(2256) bit-serial multiplier on elliptic curve point operations. A 3-stage pipelined version of the Massy-Omura GF(2m) normal basis multiplier for 160 lesm les 256 was studied in terms of area overhead and throughput improvement. Simple gate area and delay models were used to estimate the throughput of the pipelined and the non-pipelined multipliers. The proposed pipelined architecture has been shown to have a significant improvement in throughput allowing a single 3-stage pipelined multiplier to have higher throughput than an architecture employing three parallel non-pipelined multipliers. The AT2 performance metric has shown an even more significant improvement.

An expandable Montgomery modular multiplication processor

Several public-key cryptographic systems (Schneier, 1996) make heavy use of modular multiplication. A design for expandable modular multiplication hardware is proposed. This design allows for cascading the hardware if larger moduli are required. The proposed design uses a Montgomery modular multiplication algorithm (Koc et al, IEEE Micro, pp. 26-33, June 1996).

Stochastic evolution algorithm for technology mapping

A new technology mapper (SELF-Map) for Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) is described. SELF-Map is based on the Stochastic Evolution (SE) algorithm. The state space model of the problem is defined and suitable cost function which allows optimization for area, delay, or area-delay combinations is proposed. Experimental results show that SELF-Map has an overall better performance compared to other algorithms reported in the literature.

GENERALIZED ALGORITHMS FOR BINARY MODULO MULTIPLICATION AND MULTIPLICATION-DIVISION

This paper, describes novel algorithms and circuitry for binary modulo-multiplication and combined multiplication-division. Unlike the commonly used Montgomery modular multiplier, no domain mapping is needed for the input operands or the output result. Further, the new algorithms work for both even and odd moduli. The combined multiplication-division algorithm produces the quotient as well as the remainder thus allowing the implementation of simple multiplier-dividers. The proposed algorithm uses left shift-based multiplication while maintaining the size of the intermediate running product contained by interleaving reduction and multiplication operations. Reduction is determined by examining only the two most significant bits of the running product if Carry-Propagate adders are used or the 3 most significant bits if Carry-Save Adders are used. Hardware implementations of the proposed algorithms show area and delay figures comparable to those of Montgomery.

Double-rail encoded self-timed adder with matched delays

An efficient self-timed adder with low area overhead and efficient acknowledge slack time is proposed. The adder uses double-rail encoding of the carry signals as well as process-tracking matching delays to guarantee proper generation of the completion signal.

Parallelism analysis and extraction of digital signal processing algorithms

A new approach for parallelism analysis and extraction of digital signal processing algorithms is introduced. The high level description of the input is given in CIRCAL. A dependency graph of the problem is constructed to check existence of cycles. Loops in the dependency graph are parallelized. The approach is illustrated by an example.<<ETX>>

An intelligent EPROM silicon compiler

The authors describe an intelligent EPROM silicon compiler. The compiler accepts high-level specifications of the required EPROM design together with technology and process information and produces CMOS mask geometries for all layers. A knowledge-based kernel determines the chip architecture and required circuit blocks and calls appropriate module generators for each block. Routing algorithms are then used to connect these blocks into a full chip.<<ETX>>