Alan Colli

Controlling subnanometer gaps in plasmonic dimers using graphene

Graphene is used as the thinnest possible spacer between gold nanoparticles and a gold substrate. This creates a robust, repeatable, and stable subnanometer gap for massive plasmonic field enhancements. White light spectroscopy of single 80 nm gold nanoparticles reveals plasmonic coupling between the particle and its image within the gold substrate. While for a single graphene layer, spectral doublets from coupled dimer modes are observed shifted into the near-infrared, these disappear for increasing numbers of layers. These doublets arise from charger-transfer-sensitive gap plasmons, allowing optical measurement to access out-of-plane conductivity in such layered systems. Gating the graphene can thus directly produce plasmon tuning.

Low-temperature synthesis of ZnSe nanowires and nanosaws by catalyst- assisted molecular-beam epitaxy

Single-crystal ZnSe nanowires are grown on a prepatterned gold catalyst by molecular-beam epitaxy. Optimum selectivity and maximum nanowire densities are obtained for growth temperatures in the range 400–450°C, but gold-assisted growth is demonstrated for temperatures as low as 300°C. This suggests a diffusion process on/through the catalyst particle in the solid state, in contrast to the commonly assumed liquid phase growth models. Straight wires, as thin as 10nm, nucleate together with thicker and saw-like structures. A gold particle is always found at the tip in both cases.

Deep reactive ion etching as a tool for nanostructure fabrication

Deep reactive ion etching (DRIE) is investigated as a tool for the realization of nanostructures and architectures, including nanopillars,siliconnanowires or carbon nanotubes on Si nanopillars, nanowalls, and nanonetworks. The potential of combining top-down fabrication methods with the bottom-up synthesis of one-dimensional nanocomponents is assessed. The field-emission properties of carbon nanotubes/Si pillars hybrid structures are measured, as well as the transport properties of large-area nanowires obtained via nanowire lithography. The potential of DRIE for the fabrication of three-dimensional nanostructures is also revealed.

Thermal and chemical vapor deposition of Si nanowires: Shape control, dispersion, and electrical properties

We investigate and compare complementary approaches to SiNW production in terms of yield, morphology control, and electrical properties. Vapor-phase techniques are considered, including chemical vapor deposition (with or without the assistance of a plasma) and thermal evaporation. We report Au-catalyzed nucleation of SiNWs at temperatures as low as 300°C using SiH4 as precursor. We get yields up to several milligrams by metal-free condensation of SiO powders. For all processes, we control the final nanostructure morphology. We then report concentrated and stable dispersions of SiNWs in solvents compatible with semiconducting organic polymers. Finally, we investigate the electrical response of intrinsic SiNWs grown by different methods. All our SiNWs exhibit p-type behavior and comparable performance, though in some cases ambipolar devices are observed. Thus, processing and morphology, rather than the growth technique, are key to achieve optimal samples for applications.

Ion Beam Doping of Silicon Nanowires

We demonstrate n- and p-type field-effect transistors based on Si nanowires (SiNWs) implanted with P and B at fluences as high as 10(15) cm (-2). Contrary to what would happen in bulk Si for similar fluences, in SiNWs this only induces a limited amount of amorphization and structural disorder, as shown by electrical transport and Raman measurements. We demonstrate that a fully crystalline structure can be recovered by thermal annealing at 800 degrees C. For not-annealed, as-implanted NWs, we correlate the onset of amorphization with an increase of phonon confinement in the NW core. This is ion-dependent and detectable for P-implantation only. Hysteresis is observed following both P and B implantation.

Raman scattering on silicon nanowires : The thermal conductivity of the environment determines the optical phonon frequency

We studied the Raman spectra of silicon nanowires as a function of excitation power for various ambient gases. For a given excitation power, we find that the gas thermal conductivity determines the wire temperature, which can be detected by a change in phonon frequency. This shows that the redshift of the optical phonon in silicon nanowires compared to bulk silicon is mainly due to the lower thermal conductivity of nanowires and an increase in laser heating. The spectra of nanowires allow distinguishing gases on the basis of their thermal conductivity.

Nanowire Lithography on Silicon

Nanowire lithography (NWL) uses nanowires (NWs), grown and assembled by chemical methods, as etch masks to transfer their one-dimensional morphology to an underlying substrate. Here, we show that SiO2 NWs are a simple and compatible system to implement NWL on crystalline silicon and fabricate a wide range of architectures and devices. Planar field-effect transistors made of a single SOI-NW channel exhibit a contact resistance below 20 kOmega and scale with the channel width. Further, we assess the electrical response of NW networks obtained using a mask of SiO2 NWs ink-jetted from solution. The resulting conformal network etched into the underlying wafer is monolithic, with single-crystalline bulk junctions; thus no difference in conductivity is seen between a direct NW bridge and a percolating network. We also extend the potential of NWL into the third dimension, by using a periodic undercutting that produces an array of vertically stacked NWs from a single NW mask.

Top-Gated Silicon Nanowire Transistors in a Single Fabrication Step

Top-gated silicon nanowire transistors are fabricated by preparing all terminals (source, drain, and gate) on top of the nanowire in a single step via dose-modulated e-beam lithography. This outperforms other time-consuming approaches requiring alignment of multiple patterns, where alignment tolerances impose a limit on device scaling. We use as gate dielectric the 10-15 nm SiO(2) shell naturally formed during vapor-transport growth of Si nanowires, so the wires can be implemented into devices after synthesis without additional processing. This natural oxide shell has negligible leakage over the operating range. Our single-step patterning is a most practical route for realization of short-channel nanowire transistors and can be applied to a number of nanodevice geometries requiring nonequivalent electrodes.

Selective growth of ZnSe and ZnCdSe nanowires by molecular beam epitaxy

Controlled growth of ZnSe and ZnCdSe nanowires is demonstrated by molecular beam epitaxy using Au or Ag catalyst films in the temperature range 400–550 °C. The highest density of small-diameter (10 nm), highly-crystalline ZnSe nanowires is achieved by using Au at 400 °C. Direct growth onto transmission electron microscope grids clearly indicates a tip-growth regime. Pre-patterning of the catalyst film allows highly selective ZnSe deposition as probed by photoluminescence and Raman spectroscopy. In similar conditions, the addition of Cd vapour in the MBE reactor allows the synthesis of ZnCdSe ternary nanowires.

Room temperature single electron charging in single silicon nanochains

Single-electron charging effects are observed at room temperature in single Si nanochains. The nanochains, grown by thermal evaporation of SiO solid sources, consist of a series of Si nanocrystals ∼10nm in diameter, separated by SiO2 regions. Multiple step Coulomb staircase current-voltage characteristics are observed at 300K in devices using single, selected, nanochains. The characteristics are investigated using a model where the nanochain forms a multiple tunnel junction. The single-electron charging energy for a nanocrystal within the multiple-tunnel junction is EC=e2∕2Ceff∼0.32eV, ∼12kBT at 300K.