Albert E. Ruehli

Efficient Capacitance Calculations for Three-Dimensional Multiconductor Systems

The design and packaging of integrated circuits requires the calculation of capacitances for three-dimensional conductors located on parallel planes. An integral-equation (IE) computer-solution technique is presented, which provides accurate results. The solution technique minimizes computer storage requirements while maintaining calculating efficiency computation times.

Circuit models for three-dimensional geometries including dielectrics

The partial element equivalent circuit (PEEC) approach has proved useful for modeling many different electromagnetic problems. The technique can be viewed as an approach for the electrical circuit modeling for arbitrary 3-D geometries. Recently, the authors extended the method to include retardation with the rPEEC models. So far the dielectrics have been taken into account only in an approximate way. In this work, they generalize the technique to include arbitrary homogeneous dielectric regions. The new circuit models are applied in the frequency as well as the time domain. The time solution allows the modeling of VLSI systems which involve interconnects as well as nonlinear transistor circuits. >

Methods for linear systems of circuit delay differential equations of neutral type

Delay differential equations (DDEs) occur in many different fields including circuit theory. Circuits which include delayed elements have become more important due to the increase in performance of VLSI systems. The two types of circuits which include elements with delay are transmission lines and partial element equivalent circuits. The solution of systems which include these circuit elements are performed with solvers similar to conventional ODE circuits simulators. Since DDE solvers are more fragile with respect to stability, we investigate the conditions for contractivity and determine sufficient conditions for the asymptotic stability of the zero solution by utilizing a suitable reformulation of the system.

Nonorthogonal PEEC formulation for time- and frequency-domain EM and circuit modeling

Electromagnetic solvers based on the partial element equivalent circuit (PEEC) approach have proven to be well suited for the solution of combined circuit and EM problems. The inclusion of all types of Spice circuit elements is possible. Due to this, the approach has been used in many different tools. Most of these solvers have been based on a rectangular or Manhattan representation of the geometries. In this paper, we systematically extend the PEEC formulation to nonorthogonal geometries since many practical EM problems require a more general formulation. Importantly, the model given in this paper is consistent with the classical PEEC model for rectangular geometries. Some examples illustrating the application of the approach are given for both the time and frequency domain.

Three-dimensional interconnect analysis using partial element equivalent circuits

Two extensions to the partial element equivalent circuit (PEEC) approach for interconnect modeling are presented. First, retardation, the effect of the finite speed of electromagnetic interactions, is included. Second, PEEC is extended to include a circuit model of finite-size homogeneous dielectrics. It is shown that the retarded PEEC formulation with the new dielectric model is equivalent to a full-wave solution of Maxwells equation. Since they can be combined with linear and nonlinear circuits, the resulting models are more flexible than existing full-wave solvers. >

Progress in the methodologies for the electrical modeling of interconnects and electronic packages

The rapid growth of the electrical modeling and analysis of the interconnect structure, both at the electronic chip and package level, can be attributed to the increasing importance of the electromagnetic properties of the interconnect circuit on the overall electrical performance of state-of-the-art very large scale integration (VLSI) systems. With switching speeds well below 1 ns in todays gigahertz processors, and VLSI circuit complexity exceeding the 100 million transistors per chip mark, power and signal distribution is characterized by multigigahertz bandwidth pulses propagating through a tightly coupled three-dimensional wiring structure that exhibits resonant behavior at the upper part of the spectrum. Consequently, in addition to the inductive and capacitive coupling, present between adjacent wires across the entire frequency bandwidth, distributed electromagnetic effects, manifested as interconnect-induced delay, reflection, radiation, and long-range nonlocal coupling, become prominent at high frequencies, with a decisive impact of overall system performance. The electromagnetic nature of such high-frequency effects, combined with the geometric complexity of the interconnect structure, make the electrical design of todays performance-driven systems extremely challenging. Its success is heavily dependent on the availability of sophisticated electromagnetic modeling methodologies and computer-aided design tools. This paper presents an overview of the different approaches employed today for the development of an electromagnetic modeling and simulation framework that can effectively tackle the complexity of the interconnect circuit and facilitate its design. In addition to identifying the current state of the art, an assessment is given of the challenges that lie ahead in the signal integrity-driven electrical design of tomorrows performance- and/or portability-driven, multifunctional ULSI systems.

Transient analysis of lossy transmission lines: an efficient approach based on the method of Characteristics

This paper is devoted to transient analysis of lossy transmission lines characterized by frequency-dependent parameters. A public dataset of parameters for three line examples (a module, a board, and a cable) is used, and a new example of on-chip interconnect is introduced. This dataset provides a well established and realistic benchmark for accuracy and timing analysis of interconnect analysis tools. Particular attention is devoted to the intrinsic consistency and causality of these parameters. Several implementations based on generalizations of the well-known method-of-characteristics are presented. The key feature of such techniques is the extraction of the line modal delays. Therefore, the method is highly optimized for long interconnects characterized by significant propagation delay. Nonetheless, the method is also successfully applied here to a short high/loss on-chip line, for which other approaches based on lumped matrix rational approximations can also be used with high efficiency. This paper shows that the efficiency of delay extraction techniques is strongly dependent on the particular circuit implementation and several practical issues including generation of rational approximations and time step control are discussed in detail.

Systematic development of transmission-line models for interconnects with frequency-dependent losses

This paper presents a new method for the extraction of the frequency-dependent, per-unit-length (p.u.l.) resistance, and inductance parameters of multiconductor interconnects. The proposed extraction methodology is based on a new formulation of the magneto-quasi-static problem that allows lossy ground planes of finite thickness to be modeled rigorously. The formulation is such that the p.u.l. impedance matrix for the multiconductor interconnect is extracted directly at a prescribed frequency. Once the matrix has been calculated over the bandwidth of interest, rational function representations of its elements are generated through a robust matrix curve-fitting process. Such a formulation enables subsequent transient analysis of interconnects through a variety of approaches. Direct incorporation of the rational function model into a general-purpose circuit simulator and a standalone multiconductor-transmission-line simulator is demonstrated.

Full-wave PEEC time-domain method for the modeling of on-chip interconnects

With the advances in the speed of high-performance chips, inductance effects in some on-chip interconnects have become significant. Specific networks such as clock distributions and other highly optimized circuits are especially impacted by inductance. Several difficult aspects have to be overcome to obtain valid waveforms for problems where inductances contribute significantly. Mainly, the geometries are very complex and the interactions between the capacitive and inductive currents have to be taken into account simultaneously. In this paper, we show that a full-wave partial element equivalent circuit method, which includes the delays among the partial elements, leads to an efficient solver enabling the analysis of large meaningful problems. Applying this method to several examples leads to helpful insights for realistic very large scale integration wiring problems. It is shown in this paper that the impact overshoot, reflections, and inductive coupling are critical for the design of critical on-chip interconnects.

Capacitance models for integrated circuit metallization wires

New concepts are introduced relating aspects of circuit theory to the multicapacitances which can be obtained from a computer program for multiconductor geometries. These concepts are applied to the wiring of an integrated circuit chip. Capacitances are found for crossovers, vias, and right angle bends for a realistic geometry.