Albert Kwon

Cultivation of Human Embryonic Stem Cells Without the Embryoid Body Step Enhances Osteogenesis In Vitro

Osteogenic cultures of embryonic stem cells (ESCs) are predominately derived from three‐dimensional cell spheroids called embryoid bodies (EBs). An alternative method that has been attempted and merits further attention avoids EBs through the immediate separation of ESC colonies into single cells. However, this method has not been well characterized and the effect of omitting the EB step is unknown. Herein, we report that culturing human embryonic stem cells (hESCs) without the EB stage leads to a sevenfold greater number of osteogenic cells and to spontaneous bone nodule formation after 10–12 days. In contrast, when hESCs were differentiated as EBs for 5 days followed by plating of single cells, bone nodules formed after 4 weeks only in the presence of dexamethasone. Furthermore, regardless of the inclusion of EBs, bone matrix formed, including cement line matrix and mineralized collagen, which displayed apatitic mineral (PO4) with calcium‐to‐phosphorous ratios similar to those of hydroxyapatite and human bone. Together these results demonstrate that culturing hESCs without an EB step can be used to derive large quantities of functional osteogenic cells for bone tissue engineering.

Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM

Oblivious RAM (ORAM) is a cryptographic primitive that hides memory access patterns as seen by untrusted storage. Recently, ORAM has been architected into secure processors. A big challenge for hardware ORAM schemes is how to efficiently manage the Position Map (PosMap), a central component in modern ORAM algorithms. Implemented naively, the PosMap causes ORAM to be fundamentally unscalable in terms of on-chip area. On the other hand, a technique called Recursive ORAM fixes the area problem yet significantly increases ORAMs performance overhead. To address this challenge, we propose three new mechanisms. We propose a new ORAM structure called the PosMap Lookaside Buffer (PLB) and PosMap compression techniques to reduce the performance overhead from Recursive ORAM empirically (the latter also improves the construction asymptotically). Through simulation, we show that these techniques reduce the memory bandwidth overhead needed to support recursion by 95%, reduce overall ORAM bandwidth by 37% and improve overall SPEC benchmark performance by 1.27x. We then show how our PosMap compression techniques further facilitate an extremely efficient integrity verification scheme for ORAM which we call PosMap MAC (PMMAC). For a practical parameterization, PMMAC reduces the amount of hashing needed for integrity checking by >= 68x relative to prior schemes and introduces only 7% performance overhead. We prototype our mechanisms in hardware and report area and clock frequency for a complete ORAM design post-synthesis and post-layout using an ASIC flow in a 32~nm commercial process. With 2 DRAM channels, the design post-layout runs at 1~GHz and has a total area of .47~mm2. Depending on PLB-specific parameters, the PLB accounts for 10% to 26% area. PMMAC costs 12% of total design area. Our work is the first to prototype Recursive ORAM or ORAM with any integrity scheme in hardware.

PrORAM: dynamic prefetcher for oblivious RAM

Oblivious RAM (ORAM) is an established technique to hide the access pattern to an untrusted storage system. With ORAM, a curious adversary cannot tell what address the user is accessing when observing the bits moving between the user and the storage system. All existing ORAM schemes achieve obliviousness by adding redundancy to the storage system, i.e., each access is turned into multiple random accesses. Such redundancy incurs a large performance overhead.Although traditional data prefetching techniques successfully hide memory latency in DRAM based systems, it turns out that they do not work well for ORAM because ORAM does not have enough memory bandwidth available for issuing prefetch requests. In this paper, we exploit ORAM locality by taking advantage of the ORAM internal structures. While it might seem apparent that obliviousness and locality are two contradictory concepts, we challenge this intuition by exploiting data locality in ORAM without sacrificing security. In particular, we propose a dynamic ORAM prefetching technique called PrORAM (Dynamic Prefetcher for ORAM) and comprehensively explore its design space. PrORAM detects data locality in programs at runtime, and exploits the locality without leaking any information on the access pattern. Our simulation results show that with PrORAM, the performance of ORA M can be significantly improved. PrORAM achieves an average performance gain of 20% over the baseline ORA M for memory intensive benchmarks among Splash2 and 5.5% for SP EC06 workloads. The peiformance gain for YCSB and TPCC in DBMS benchmarks is 23.6% and 5% respectively. On average, PrORAM offers twice the performance gain than that offered by a static super block scheme.

A Low-Latency, Low-Area Hardware Oblivious RAM Controller

We build and evaluate Tiny ORAM, an Oblivious RAM prototype on FPGA. Oblivious RAM is a cryptographic primitive that completely obfuscates an applications data, access pattern and read/write behavior to/from external memory (such as DRAM or disk). Tiny ORAM makes two main contributions. First, by removing an algorithmic bottleneck in prior work, Tiny ORAM is the first hardware ORAM design to support arbitrary block sizes (e.g. 64 Bytes to 4096 Bytes). With a 64-Byte block size, Tiny ORAM can finish an access in 1.4μs, over 40× faster than the prior-art implementation. Second, through novel algorithmic and engineering-level optimizations, Tiny ORAM reduces the number of symmetric encryption operations by ~3× compared to a prior work. Tiny ORAM is also the first design to implement and report real numbers for the cost of symmetric encryption in hardware ORAM constructions. Putting it together, Tiny ORAM requires 18381 (5%) LUTs and 146 (13%) Block RAM on a Xilinx XC7VX485T FPGA, including the cost of encryption.

Design of a compact, battery powered, and fiber optic controlled remotely operated vehicle

Developed for the 4 Annual Marine Advanced Technology Education (MATE) Centers remotely operated vehicle (ROV) competition, Tim the ROV was designed and built by MITs ROV team to compete in the Explorer Class division. Capable of operating at depths of 40 feet and completing tasks such as fluid collection, temperature measurements, and object retrieval in less than 30 minutes, Tim was designed to be small and highly maneuverable. To aid in maneuverability, Tim is equipped with on-board power and a passive-spooling, single-strand fiber optic tether. Tims compact layout and powerful thrusters also contribute to the main design goal - build a small, highly maneuverable ROV capable of competing in the MATE ROV competition.

DynaFlow: An Efficient Website Fingerprinting Defense Based on Dynamically-Adjusting Flows

Website fingerprinting attacks enable a local adversary to determine which website a Tor user visits. In recent years, several researchers have proposed defenses to counter these attacks. However, these defenses have shortcomings: many do not provide formal guarantees of security, incur high latency and bandwidth overheads, and require a frequently-updated database of website traffic patterns. In this work, we introduce a new countermeasure, DynaFlow, based on dynamically-adjusting flows to protect against website fingerprinting. DynaFlow provides a similar level of security as current state-of-the-art while being over 40% more efficient. At the same time, DynaFlow does not require a pre-established database and extends protection to dynamically-generated websites.

Private Online Communication; Highlights in Systems Verification

First, Albert Kwon provides an overview of recent systems for secure and private communication. Second, James Wilcox takes us on a tour of recent advances in verified systems design.