Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Alejandro José Cabrera Sarmiento is active.

Publication


Featured researches published by Alejandro José Cabrera Sarmiento.


Journal of Cryptographic Engineering | 2016

AES T-Box tampering attack

Alejandro Cabrera Aldaya; Alejandro José Cabrera Sarmiento; Santiago Sánchez-Solano

The use of embedded block memories (BRAMs) in Xilinx FPGA devices makes it possible to store the T-Boxes that are employed to implement the AES block cipher’s SubBytes and MixColumns operations. Several studies into BRAM resistance to side-channel attacks have been reported in the literature, whereas this paper presents a novel attack based on tampering the BRAMs storing the T-Boxes. This approach allows recovering the key using a ciphertext-only attack for all AES key sizes. The complexity of the attack makes it completely feasible. The attack was mounted against previously reported FPGA-based AES implementations, taking into account the different design criteria used in each case and focusing mainly on the implementation of the final round of the AES algorithm, which plays a crucial role in the analysis. Three different final round implementations extracted from well-known existing architectures are analyzed in this work. The paper also discusses some countermeasures with regard to security, performance and FPGA resource utilization. The attack is presented against FPGA-based implementations but it can be extended to software architectures as well.


International Journal of Circuit Theory and Applications | 2017

Side-channel analysis of the modular inversion step in the RSA key generation algorithm

Alejandro Cabrera Aldaya; Raudel Cuiman Márquez; Alejandro José Cabrera Sarmiento; Santiago Sánchez-Solano

This paper studies the security of the RSA key generation algorithm with regard to side-channel analysis and presents a novel approach that targets the simple power analysis (SPA) vulnerabilities that may exist in an implementation of the binary extended Euclidean algorithm (BEEA). The SPA vulnerabilities described, together with the properties of the values processed by the BEEA in the context of RSA key generation, represent a serious threat for an implementation of this algorithm. It is shown that an adversary can disclose the private key employing only one power trace with a success rate of 100 % – an improvement on the 25% success rate achieved by the best side-channel analysis carried out on this algorithm. Two very different BEEA implementations are analyzed, showing how the algorithm’s SPA leakages could be exploited. Also, two countermeasures are discussed that could be used to reduce those SPA leakages and prevent the recovery of the RSA private key. Copyright


Journal of Cryptographic Engineering | 2017

SPA vulnerabilities of the binary extended Euclidean algorithm

Alejandro Cabrera Aldaya; Alejandro José Cabrera Sarmiento; Santiago Sánchez-Solano


Revista Científica de Ingeniería Electrónica, Automática y Comunicaciones ISSN: 1815-5928 | 2011

Diseño de bloques de convolución para procesado de imágenes con FPGA

Luis Manuel Garcés Socarrás; Alejandro José Cabrera Sarmiento; Santiago Sánchez Solano; Piedad Brox Jiménez


Revista Facultad De Ingenieria-universidad De Antioquia | 2013

Library for model-based design of image processing algorithms on FPGAs

Luis Manuel Garcés-Socarrás; Santiago Sánchez-Solano; Piedad Brox Jiménez; Alejandro José Cabrera Sarmiento


Ingeniería electrónica, automática y comunicaciones | 2003

Arquitectura Eficiente para la Implementación Hardware de Sistemas de Inferencia Difusos

Alejandro José Cabrera Sarmiento; Santiago Sánchez Solano; Carlos Jesús Jiménez Fernández; Angel Barriga Barros; María Iluminada Baturone Castillo


III Congreso Internacional de Ingeniería Informática y Sistemas de Información | 2016

VULNERABILIDAD DEL ALGORITMO AES ANTE MODIFICACIÓN DE LAS T-BOX

Alejandro Cabrera Aldaya; Alejandro José Cabrera Sarmiento; Santiago Sánchez Solano


Revista Ingeniería Electrónica, Automática y Comunicaciones ISSN: 1815-5928 | 2013

Prototipado rápido de sistemas de procesado de vídeo basados en el VFBC de Xilinx

Luis Manuel Garcés Socarrás; Santiago Sánchez Solano; Piedad Brox Jiménez; Alejandro José Cabrera Sarmiento


Revista Ingeniería Electrónica, Automática y Comunicaciones ISSN: 1815-5928 | 2013

Diseño de bloques para el procesado de imágenes en lenguaje de descripción de hardware

Elias Augusto Perdomo Hourné; Luis Manuel Garcés-Socarrás; Alejandro José Cabrera Sarmiento


Revista Facultad De Ingenieria-universidad De Antioquia | 2013

Biblioteca para diseño basado en modelos de algoritmos de procesado de imágenes en FPGA

Luis Manuel Garcés-Socarrás; Santiago Sánchez-Solano; Piedad Brox Jiménez; Alejandro José Cabrera Sarmiento

Collaboration


Dive into the Alejandro José Cabrera Sarmiento's collaboration.

Top Co-Authors

Avatar

Alejandro Cabrera Aldaya

Instituto Politécnico Nacional

View shared research outputs
Top Co-Authors

Avatar

Santiago Sánchez Solano

Spanish National Research Council

View shared research outputs
Top Co-Authors

Avatar

Piedad Brox Jiménez

Spanish National Research Council

View shared research outputs
Top Co-Authors

Avatar

Santiago Sánchez-Solano

Spanish National Research Council

View shared research outputs
Top Co-Authors

Avatar
Top Co-Authors

Avatar

Raudel Cuiman Márquez

Instituto Politécnico Nacional

View shared research outputs
Top Co-Authors

Avatar

Ander Torres López

Instituto Politécnico Nacional

View shared research outputs
Top Co-Authors

Avatar

Humberto Díaz Pando

Instituto Politécnico Nacional

View shared research outputs
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Researchain Logo
Decentralizing Knowledge