Aleksandar Radic

Minimum deviation digital controller IC for single and two phase dc-dc switch-mode power supplies

A digital PWM voltage mode controller integrated circuit (IC) for high-frequency dc-dc switching converters achieving virtually minimum possible, i.e. optimum, output voltage deviation to load transients is introduced. The IC is implemented with simple hardware, requiring small silicon area, and can operate as a single-phase or a two-phase controller. To minimize the area and eliminate known mode transition problems of the optimal response controllers, two novel blocks are combined. Namely, an asynchronous track-and-hold analog-to-digital converter (ADC) and a ¿large-small¿ signal compensator are implemented. The ADC utilizes a pre-amplifier and only four comparators having approximately eight times smaller silicon area and power consumption than an equivalent windowed flash architecture. The ¿large-small¿ signal compensator consists of two parts, a digital PID minimizing small variations and a zero-current detection-based compensator suppressing large load transients. The large-signal compensator requires no extra calculations and has a low sensitivity to parameter variations. It utilizes a synchronization algorithm and the PID calculation results to obtain a bumpless mode transition and stable response to successive load transients. The IC occupying only 0.26 mm2 silicon area is implemented in a CMOS 0.18¿m process and its minimum deviation response is verified with a single and dual-phase 12 V-to-1.8 V, 500 kHz 60/120 W buck converter.

Minimum-Deviation Digital Controller IC for DC–DC Switch-Mode Power Supplies

This paper introduces a hardware-efficient digital controller integrated circuit (IC) for single- and two-phase dc-dc converters that recovers from load transients with virtually minimum possible output voltage deviation. In steady state, the IC behaves as a conventional voltage-mode pulsewidth modulation controller. During load changes, it enters transient suppression mode that utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power, to seamlessly recover back to the steady state without exposing components to a high-current stress. To further minimize the area and power consumption of the IC, an asynchronous track-and-hold analog-to-digital converter (ADC) is developed. The ADC utilizes only one preamplifier and four comparators having approximately ten times smaller silicon area and power consumption than a comparable windowed flash ADC. To compensate effects of converter losses and system delays on the controller operation, the IC also incorporates duty ratio correction logic and dual-extreme point-based detection. The entire IC is implemented in a CMOS 0.18-μm process on a 0.26-mm2 silicon area, which is comparable to the state-of-the-art analog solutions. The functionality of the controller is tested with both single- and two-phase commercial 12-1.8 V, 500-kHz 60/120-W buck converter power stages. The results demonstrate seamless transition to the steady state with virtually minimum output voltage deviation. For the experimental system, this deviation is about four times smaller than that of a fast PID compensator having a one-tenth of the switching frequency bandwidth.

Buck Converter With Merged Active Charge-Controlled Capacitive Attenuation

This letter introduces a converter and a complementary digital controller that, compared to conventional buck, have a smaller output filter volume, improved dynamic response, and lower switching losses. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single digital controller governs operation of the both stages. The controller utilizes the inductor current to regulate the center tap voltage, through a charge-control algorithm. During transients, the attenuator is bypassed, so the inductor current slew rate is improved. Experiments with a 5-1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.

A 10 MHz mixed-signal CPM controlled DC-DC converter IC with novel gate swing circuit and instantaneous efficiency optimization

This paper introduces a mixed-signal peak current-programmed mode controlled 10 MHz dc-dc converter integrated circuit (IC) for low-power applications. The IC combines segmented power transistors, gate drivers and the main functional blocks of a multi-mode controller. Based on the information about the peak transistor current, obtained from the voltage loop, the controller instantaneously changes the number of segments, gate drive voltage, or switches to pulse-frequency modulation, such that for each operating point efficiency is optimized. To obtain reliable operation at such a high switching frequency and achieve efficiency optimization novel architecture of gate swing circuit is combined with modifications of known designs of other functional blocks. Experimental verification of a 0.6 W buck converter IC, fabricated in a 0.13 µm process, demonstrate the peak efficiency of an 83%, near time-optimal dynamic response, and up to a 20% efficiency improvement due to the action of the efficiency optimization controller.

Self-tuning mixed-signal optimal controller with improved load transient waveform detection and smooth mode transition for DC-DC converters

A hardware efficient optimum-deviation voltage mode controller with a fast and noise-insensitive detection of the key voltage waveform points during load transients is introduced. To reduce the effects of noise and delays on the detection, a two extreme point detector with a voltage tracking window is introduced. In addition, an on-line algorithm for the compensation of load-dependent duty ratio variations effecting stability of optimal controllers is developed. The effectiveness of the system is verified with a 12V-to-1.6V/50 W, 500 kHz buck converter demonstrating about 30% smaller voltage deviation compared to the conventional optimal controller.

High-power density hybrid converter topologies for low-power Dc-Dc SMPS

This paper gives a review of several emerging dc-dc converter topologies that combine capacitor-based and inductive converters in single hybrid converter structures. It is shown that, compared to the conventional topologies, the hybrid buck converters allow for a drastic reduction of the inductive components while minimizing switching losses and improving the overall power processing efficiency. Therefore, the hybrid converters result in a higher power density. As examples, buck with merged capacitive divider, a two-phase interleaved buck, and a differential buck-based multi-output power module for mobile applications are shown. The presented converters have up to four times smaller inductor volume and, at the same time, about 12% lower losses.

Noninvasive self-tuning output capacitor time constant estimator for low power digitally controlled DC-DC converters

A passive and hardware efficient output capacitor time-constant estimator for digitally controlled dc-dc converters is introduced. The estimator emulates the equivalent RC circuit of the output capacitor with a much smaller version, placed in parallel, and adjusts its own resistance until the two circuits have the same time-constant. The adjustment is based on a very simple zero voltage crossing detection and synchronization with the digital pulse-width modulator operation. The effectiveness of the proposed estimator is illustrated using a 5V-to-1V/5A, 500kHz buck converter demonstrating accuracy within a few tens of ns in the detection of capacitor zero current crossing points.

Adaptive switching frequency scaling digital controller for improving efficiency of battery powered dc-dc converters

This paper introduces a practical system for improving efficiency of low power dc-dc converters regulated by digital voltage-mode PWM controllers. Depending on the input voltage, the controller adaptively changes the switching frequency, thus minimizing related losses while maintaining tight output voltage regulation and constraining electromagnetic interference (EMI) caused by the variable frequency operation. The presented architecture, whose key new element is alldigital adaptive clock and spread spectrum generator, can be implemented in the latest CMOS technologies and, as such, is well-suited for on-chip integration in portable battery-powered applications. The effectiveness of the system is verified with a 2.1 V/ 5 W buck prototype, where the input voltage ranges between 2.75 V and 5.5 V. The results show that, for an adaptive frequency regulation in the range between 780 kHz and 2 MHz, loss reduction of up to 18% is achieved.

Low-volume stackable flyback converter with near minimum deviation controller

This paper introduces a flyback-based low-volume modular converter and complementary mixed-signal controller that provide input voltage and output current sharing as well as near optimal transient response. This serial-input paralleloutput switch-mode power supply (SMPS) is well suited for high-step down ratio applications where, compared to a conventionally used multi-phase buck, it requires a smaller output filter volume, lower MOSFET blocking voltages, and provides better dynamic response. The stackable flyback also has better power processing efficiency and provides inherent passive current sharing. These advantages are achieved by utilizing low-voltage flyback cells and a novel implementation of minimum deviation control method. Experiments with a 12-to-1-V, 4-A, 500kHz 2-cell stacked flyback converter prototype show that, compared to an equivalent 12-V 2-phase conventional buck with approximately the same inductor volume, the introduced converter has 14% smaller output capacitor, up to 40% lower power losses, and 33% faster transient response.

Synchronized Zero-Crossing-Based Self-Tuning Capacitor Time-Constant Estimator for Low-Power Digitally Controlled DC–DC Converters

A hardware efficient method and system for estimating the time constant and measuring the current of the output capacitors in digitally controlled switch-mode power supplies is introduced. The estimator emulates the equivalent RC circuit of the output capacitor with a much smaller version, placed in parallel, and adjusts its own resistance until the two circuits have the same time constant. The adjustment is based on a novel zero voltage crossing detection method and on synchronization with the digital pulse-width modulator operation. The effectiveness of the new estimator is verified with a 5 V to 1 V/5 A, 500-kHz buck converter prototype utilizing an optimal response controller. The experimental results show accuracy within a few tens of nanoseconds in the detection of capacitor zero-current crossing points, corresponding to a smaller than a 1.5% error in the time constant estimation, and, compared to an imperfectly tuned system, about 40% smaller voltage deviation during transients.