Aleksej Avramovic

Convolutional Neural Network Based Automatic Object Detection on Aerial Images

We are witnessing daily acquisition of large amounts of aerial and satellite imagery. Analysis of such large quantities of data can be helpful for many practical applications. In this letter, we present an automatic content-based analysis of aerial imagery in order to detect and mark arbitrary objects or regions in high-resolution images. For that purpose, we proposed a method for automatic object detection based on a convolutional neural network. A novel two-stage approach for network training is implemented and verified in the tasks of aerial image classification and object detection. First, we tested the proposed training approach using UCMerced data set of aerial images and achieved accuracy of approximately 98.6%. Second, the method for automatic object detection was implemented and verified. For implementation on GPGPU, a required processing time for one aerial image of size 5000 × 5000 pixels was around 30 s.

An iterative logarithmic multiplier

Digital signal processing algorithms often rely heavily on a large number of multiplications, which is both time and power consuming. However, there are many practical solutions to simplify multiplication, like truncated and logarithmic multipliers. These methods consume less time and power but introduce errors. Nevertheless, they can be used in situations where a shorter time delay is more important than accuracy. In digital signal processing, these conditions are often met, especially in video compression and tracking, where integer arithmetic gives satisfactory results. This paper presents a simple and efficient multiplier with the possibility to achieve an arbitrary accuracy through an iterative procedure, prior to achieving the exact result. The multiplier is based on the same form of number representation as Mitchells algorithm, but it uses different error correction circuits than those proposed by Mitchell. In such a way, the error correction can be done almost in parallel (actually this is achieved through pipelining) with the basic multiplication. The hardware solution involves adders and shifters, so it is not gate and power consuming. The error summary for operands ranging from 8 bits to 16 bits indicates a very low relative error percentage with two iterations only. For the hardware implementation assessment, the proposed multiplier is implemented on the Spartan 3 FPGA chip. For 16-bit operands, the time delay estimation indicates that a multiplier with two iterations can work with a clock cycle more than 150MHz, and with the maximum relative error being less than 2%.

Lossless compression of medical images based on gradient edge detection

In this paper, a novel predictive-based lossless image compression algorithm is presented. Lossless compression must be applied when data acquisition is important and expensive, as in aerial, medical and space imaging. Besides requirements of high compression ratios as much as it is possible, lossless image coding algorithms must be fast. Proposed algorithm is developed for efficient and fast processing of 12-bit medical images. Comparison with standardized lossless compression algorithm, JPEG-LS is done on a set of 12-bit medical images with different statistical features. It is shown that proposed solution can achieve approximately same bitrates as JPEG-LS even though it is much simpler.

A simple pipelined logarithmic multiplier

Digital signal processing algorithms often rely heavily on a large number of multiplications, which is both time and power consuming. However, there are many practical solutions to simplify multiplication, like truncated and logarithmic multipliers. These methods consume less time and power but introduce errors. Nevertheless, they can be used in situations where a shorter time delay is more important than accuracy. In digital signal processing, these conditions are often met, especially in video compression and tracking, where integer arithmetic gives satisfactory results. This paper presents and compare different multipliers in a logarithmic number system. For the hardware implementation assessment, the multipliers are implemented on the Spartan 3 FPGA chip and are compared against speed, resources required for implementation, power consumption and error rate. We also propose a simple and efficient logarithmic multiplier with the possibility to achieve an arbitrary accuracy through an iterative procedure. In such a way, the error correction can be done almost in parallel (actually this is achieved through pipelining) with the basic multiplication. The hardware solution involves adders and shifters, so it is not gate and power consuming. The error of proposed multiplier for operands ranging from 8 bits to 16 bits indicates a very low relative error percentage.

A simple pipelined squaring circuit for DSP

There are many digital signal processing applications where a shorter time delay of algorithms and efficient implementations are more important than accuracy. Since squaring is one of the fundamental operations widely used in digital signal processing algorithms, approximate squaring is proposed. We present a simple way of approximate squaring that allows achieving a desired accuracy. The proposed method uses the same simple combinational logic for the first approximation and correction terms. Performed analysis for various bit-length operands and level of approximation showed that maximum relative errors and average relative errors decrease significantly by adding more correction terms. The proposed squaring method can be implemented with a great level of parallelism. The pipelined implementation is also proposed in this paper. The proposed squarer achieved significant savings in area and power when compared to multiplier based squarer. As an example, an analysis of the impact of Euclidean distance calculation by approximate squaring on image retrieval is performed.

An approximate logarithmic squaring circuit with error compensation for DSP applications

The squaring function is one of the frequently used arithmetic functions in DSP, so an approximation of the squaring function is acceptable as long as this approximation corrupts the bits that are already corrupted by noise, and does not degrade application@?s performance significantly. Approximation of the squaring function can lead to significant savings in hardware and processing time. Previously proposed approximations of the squaring function include LUT-based solutions, linear interpolation of the squaring function and minimization of combinational logic. This paper proposes approximation based on a simple logarithmic interpolation of a squaring function with a simple logic block, which can be reused for the error compensation. The proposed block performs approximation of the squaring function with a shift operation and a carry-free subtraction. The proposed approximate squarer with one compensation block achieves the average relative error below 1.5% for any bit length, while maintaining a low power consumption. In order to evaluate the device utilization, the propagation delay and power consumption and to compare it with the existing solutions, we have synthesized the proposed squarer and the existing solutions for the standard cell library and 0.25@mm CMOS process parameters.

Lossless audio compression using modular arithmetic and performance-based adaptation

During the last decade, storage of audio data without losses gained on its importance due to increased necessities for high-quality audio reproduction. The second reason can be found in implementation of systems such as speech recognition which can benefit from lossless data. This paper introduces lossless audio compression algorithm based on modular arithmetic and performance based adaptation. The proposed algorithm can compress audio data in simple mode without adaptation which requires less computation, or with adaptation which is more computationally demanding but has better performance. Comparison of the proposed algorithm with available lossless audio codecs, according to compression ratio, is made on two sets of data. The first set includes various music tracks and the second set is collection of speech recordings.

Performance of texture descriptors in classification of medical images with outsiders in database

During the years image classification gained important significance in practice, especially in the fields of digital radiology, remote sensing, image retrieval, etc. Typical algorithm for image classification contains descriptor extraction phase, learning phase and testing phase. Testing phase calculates accuracy of the classifier based on predetermined set of labelled images. This paper analyse performance of texture descriptors combined with SVMs, in the case when test dataset contains images not belonging to any predetermined class. A robustness of texture descriptors on outsiders is analysed, to see if descriptor is able to separate outsiders in specific class. Medical dataset containing various radiology images is used for testing. It was shown that it is possible to separate images not belonging to any class with cost of decreased performance by few percent.

An Iterative Mitchell's Algorithm Based Multiplier

This paper presents a new multiplier with possibility to achieve an arbitrary accuracy. The multiplier is based upon the same idea of numbers representation as Mitchells algorithm, but does not use logarithm approximation. The proposed iterative algorithm is simple and efficient, achieving an error percentage as small as required, until the exact result. Hardware solution involves adders and shifters, so it is not gate and power consuming. Parallel circuits are used for error correction. The error summary for operands ranging from 8-bits to 16-bits operands indicates very low error percentage with only two parallel correction circuits.

Multispectral scene recognition based on dual convolutional neural networks.

Multispectral sensors are becoming more accessible which draws additional attention to the problem of processing and classification of multispectral images. In this research we addressed the problem of automatic scene recognition of multispectral images using convolutional neural networks with tailored architecture. More precisely, we propose and describe a special dual network architecture which is able to efficiently process multispectral images and, at the same time, use the possibilities of networks pretrained on feature-rich image dataset. Experiments showed that dual network can efficiently recognize multispectral scenes, even though a small amount of training images had been available. Comparing to the best accuracy of descriptor based method previously reported, our method made an improvement of nearly 5%, achieving the classification accuracy over 92% on benchmark multispectral scene dataset.