Alessandro Benedetti

Strain determination in silicon microstructures by combined convergent beam electron diffraction, process simulation, and micro-Raman spectroscopy

Test structures consisting of shallow trench isolation (STI) structures are fabricated using advanced silicon (Si) technology. Different process parameters and geometrical features are implemented to investigate the residual mechanical stress in the structures. A technology computer aided design homemade tool, IMPACT, is upgraded and optimized to yield strain fields in deep submicron complementary metal–oxide–semiconductor devices. Residual strain in the silicon substrate is measured with micro-Raman spectroscopy (μ-RS) and/or convergent beam electron diffraction (CBED) for large (25 μm) and medium size (2 μm), while only CBED is used for deep submicron STI (0.22 μm). We propose a methodology combining CBED and technology computer aided design (TCAD) with μ-RS to assess the accuracy of the CBED measurements and TCAD calculations on the widest structures. The method is extended to measure (by CBED) and calculate (by TCAD) the strain tensor in the smallest structures, out of the reach of the μ-RS technique....

Application of convergent beam electron diffraction to two-dimensional strain mapping in silicon devices

A method of obtaining quantitative two-dimensional (2D) maps of strain by the convergent beam electron diffraction technique in a transmission electron microscope is described. It is based on the automatic acquisition of a series of diffraction patterns generated from digital rastering the electron spot in a matrix of points within a selected area of the sample. These patterns are stored in a database and the corresponding strain tensor at each point is calculated, thus yielding a 2D strain map. An example of application of this method to cross-sectioned cells fabricated for the 0.15 μm technology of flash memories is reported.

Defect Removal, Dopant Diffusion and Activation Issues in Ion-Implanted Shallow Junctions Fabricated in Crystalline Germanium Substrates

The formation of shallow junctions in germanium substrates, compatible with deep submicron CMOS processing is discussed with respect to dopant diffusion and activation and damage removal. Examples will be discussed for B and Ga and for P and As, as typical p- and n-type dopants, respectively. While 1 to 60 s Rapid Thermal Annealing at temperatures in the range 400-650oC have been utilized, in most cases, no residual extended defects have been observed by RBS and TEM. It is shown that 100% activation of B can be achieved in combination with a Ge pre-amorphisation implant. Full activation of a P-implant can also be obtained for low-dose implantations, corresponding with immobile profiles. On the other hand, for a dose above the threshold for amorphisation, a concentration-enhanced diffusion of P occurs, while a lower percentage of activation is observed. At the same time, dose loss by P out-diffusion occurs, which can be limited by employing a SiO2 cap layer.

Convergent beam electron diffraction investigation of strain induced by Ti self-aligned silicides in shallow trench Si isolation structures

The deformation induced onto silicon by the formation of Ti self-aligned silicides (salicides) in shallow trench isolation structures has been investigated by the convergent beam electron diffraction technique (CBED) in the transmission electron microscope (TEM). The splitting of the high order Laue zone (HOLZ) lines in the CBED patterns taken in TEM cross sections close to the salicide/silicon interface has been explained assuming that the salicide grains induce a local bending of the lattice planes of the underlying matrix. This bending, which affects in opposite sense the silicon areas below adjacent grains, decreases with the distance from the interface, eventually vanishing at a depth of 300–400nm. The proposed strain field has been implemented into a fully dynamical simulation of the CBED patterns and has proved to be able to reproduce both the asymmetry of the HOLZ line splitting and the associated subsidiary fringes. This model is confirmed by the shift of a Bragg contour observed in large angle C...

The Challenges of Ge-Condensation Technique

In order to integrate Ge CMOS technology however, new techniques for manufacturing Ge substrates/channels are needed. From integration point of view it is more interesting to manufacture device-quality Ge on top of standard SOI substrates, since this could allow the combination with standard Si CMOS circuitry in the same IC. One possible way for the development of ultra thin, Ge-on-insulator layers (GeOI) for < 45 nm technology nodes is the oxidation at high temperature of SiGe layers, epitaxially grown on an SOI substrates. This fabrication method is called Ge condensation technique. The potential of Ge condensation process as a technique to manufacture thin Ge-on-Insulator layers has already been demonstrated by Takagi et al. but limited process details are available (1,2). Little is known about the mechanisms of the intermediate stages of the condensation process.

Strain and Ge concentration determinations in SiGe/Si multiple quantum wells by transmission electron microscopy methods

SiGe/Si multiple quantum wells, nominally 4 nm thick, were grown by low pressure chemical vapor deposition and the Ge distribution within the wells was studied using a variety of transmission electron microscope-based techniques. Energy-dispersive x-ray spectroscopy and electron energy-loss imaging were used to directly measure the Ge compositional profile across the SiGe wells. In addition, the average Ge concentration was deduced indirectly from measurement of the strain-induced lattice displacements in high resolution images, obtained from the relative phase shift of the Si lattice planes on either side of a SiGe well. The results from both the direct and indirect measurement techniques were compared and found to be in good agreement with one another. The Ge profiles exhibited an asymmetric shape consistent with the occurrence of Ge segregation during growth. However, the amplitude of the asymmetry indicated that an additional factor, in particular gas dwell times within the reactor, also needed to be ...

The role of preamorphization and activation for ultra shallow junction formation on strained Si layers grown on SiGe buffer

The role of amorphization during implantation, different doping impurities and thermal budget on the junction and the transistor channel regions properties were investigated. Two approaches of dopant activation discussed include: low temperature solid phase epitaxial regrowth and high temperature conventional spike. The corresponding thermal budgets didnot relax strain in the transistor channel. The results show that for rapid thermal annealing (RTA) activation only B-doped samples prove benefits.

Strain Analysis in Submicron Electron Devices by Convergent Beam Electron Diffraction

The basic features of the convergent beam electron diffraction technique (CBED) ina transmission electron microscope (TEM) for the quantitative strainan alysis of silicon nanoregions are described. Details on the procedure employed to obtain the components of the strainten sor from anexp erimental CBED patternare given. The CBED methodology has been recently applied to the analysis of straininthe field of microelectronics; as anexample, the investigationof 0.22 μm wide electrically active silicon regions, underlying silicon nitride stripes in shallow trench isolation structures for non volatile memories, is reported. It is found that the strain field can be related to the different technological steps.