Alessandro Cabrini

On-chip error correcting techniques for new-generation flash memories

In new-generation flash memories, issues such as disturbs and data retention become more and more critical as a consequence of reduced cell size and decreased oxide thickness. Furthermore, the progressive increase in the cell count within a single die tends to decrease device reliability. In particular, reliability issues turn out to be more critical in multilevel (ML) flash memories, due to the reduced spacing between adjacent programmed levels. It is therefore deemed that the use of on-chip error correction codes (ECCs) will gain widespread acceptance in large-capacity flash memories. ECCs for flash memories must have very fast and compact encoding/decoding circuitry so as to have a minimum impact on memory access time. The area penalty due to check cells must also be minimized. Moreover, specific codes must be developed for ML storage. This paper presents error control coding techniques and schemes for new-generation flash memories, focusing on ML devices. The basic concepts of error control coding are reviewed, and the on-chip ECC design procedure is analyzed. Dedicated codes such as polyvalent ECCs, able to correct data stored in ML memories working at a variable number of bits per cell, and bit-layer organized ECCs are described.

A Multi-Level-Cell Bipolar-Selected Phase-Change Memory

Phase-change memory (PCM) is becoming widely recognized as the most likely candidate to unify the many memory technologies that exist today (Lee, et al., 2007). The combination of non-volatile attributes of flash, RAM-like bit-alterability, and fast reads and writes position PCM to enable changes in the memory subsystems of cellular phones, PCs and countless embedded and consumer electronics applications. This designs multi-level cell (MLC) capabilities combined with long- term scalability reduce PCM costs as only realized before by hard disk drives. MLC technology is challenged with fitting more cell states (4 in the case of 2 bit per cell), along with distribution spreads due to process, design, and environmental variations, within a limited window. We describe a 256Mb MLC test-chip in a 90nm micro-trench (mutrench) PCM technology, and MLC endurance results from an 8Mb 0.18mum PCM test-chip with the same trench cell structure. A program algorithm achieving tightly placed inner states and experimental results illustrating distinct current distributions are presented to demonstrate MLC capability.

Dependence of resistance drift on the amorphous cap size in phase change memory arrays

Multilevel programming in phase change memories (PCMs) requires understanding of the phenomena which affect the stability of the programmed resistance levels. Although the Ge2Sb2Te5 (GST alloy) crystallization process has been extensively studied, further analysis is needed to characterize the drift of low-field amorphous-GST resistance. In this paper, we carry out a statistical analysis on an array of PCM cells so as to investigate the drift dynamics of intermediate GST resistance states. Our experimental results reveal the dependence of the drift dynamics exponent on the thickness of the amorphous cap inside the GST layer, which is ascribed to the different stresses.

Exploiting Process Variations and Programming Sensitivity of Phase Change Memory for Reconfigurable Physical Unclonable Functions

Physical unclonable function (PUF) leverages the immensely complex and irreproducible nature of physical structures to achieve device authentication and secret information storage. To enhance the security and robustness of conventional PUFs, reconfigurable physical unclonable functions (RPUFs) with dynamically refreshable challenge-response pairs (CRPs) have emerged recently. In this paper, we propose two novel physically reconfigurable PUF (P-RPUF) schemes that exploit the process parameter variability and programming sensitivity of phase change memory (PCM) for CRP reconfiguration and evaluation. The first proposed PCM-based P-RPUF scheme extracts its CRPs from the measurable differences of the PCM cell resistances programmed by randomly varying pulses. An imprecisely controlled regulator is used to protect the privacy of the CRP in case the configuration state of the RPUF is divulged. The second proposed PCM-based RPUF scheme produces the random response by counting the number of programming pulses required to make the cell resistance converge to a predetermined target value. The merging of CRP reconfiguration and evaluation overcomes the inherent vulnerability of P-RPUF devices to malicious prediction attacks by limiting the number of accessible CRPs between two consecutive reconfigurations to only one. Both schemes were experimentally evaluated on 180-nm PCM chips. The obtained results demonstrated their quality for refreshable key generation when appropriate fuzzy extractor algorithms are incorporated.

Development and analysis of a PCB vector 2-D magnetic field sensor system for electronic compasses

A high-sensitivity vector two-dimensional (2-D) magnetic sensor system for low magnetic field measurements has been realized and tested. The system, made in PCB technology, consists of a double-axis Fluxgate magnetic sensor and the readout electronic circuitry, based on second-harmonic detection. The amorphous magnetic materials Vitrovac 6025X (25 /spl mu/m thick) and Vitrovac 6025Z (20 /spl mu/m thick) were used as the ferromagnetic core of the sensor. By applying a sinusoidal excitation current having a 450-mA peak at 10 kHz with Vitrovac 6025Z, the measured magnetic sensitivity was about 1.25 mV//spl mu/T. This value seems to be adequate for the Earths magnetic field detection (/spl plusmn/60 /spl mu/T). The full-scale linearity error was about 1.5%. By using the thicker Vitrovac 6025X and a sinusoidal excitation current having a 600-mA peak at 10 kHz, a maximum sensitivity of approximately 1.68 mV//spl mu/T with a linearity error of about 1.55% full scale in the range of /spl plusmn/60 /spl mu/T were measured. Due to the use of commercially available ferromagnetic materials, the vector 2-D magnetic sensor system presented is characterized by a very simple fabrication process, thus allowing low-cost devices to be designed.

Efficiency comparison between doubler and Dickson charge pumps

The paper presents a comparison between two of the most popular charge pump structures, the Dickson charge pump and the cascade of voltage doublers. The comparison has been carried out considering power efficiency as the main parameter of interest. The discussion is supported by theoretical analysis and experimental results. To compare the two topologies, two voltage elevators were designed and integrated in a triple-well 0.18-/spl mu/m CMOS technology. The two charge pumps were designed with the same operating clock frequency, the same storage capacitance per stage, and the same number of stages (and, thus, approximately the same area). The comparison showed that the voltage doubler has the higher power efficiency by about 13%.

Voltage-Driven Partial-RESET Multilevel Programming in Phase-Change Memories

In this paper, the feasibility of partial-RESET programming in phase-change memories is experimentally investigated by considering both the single-cell behavior and the effects of parameter spreads over a memory array. The aim of this paper is to highlight advantages and drawbacks of partial-RESET programming from the viewpoint of multilevel (ML) storage. Although high reproducibility of a partial-RESET programming curve of a single cell has been observed, the parameter spreads over the array imply the need for a program-and-verify (P&V) approach to achieve the necessary accuracy for ML storage. In order to demonstrate the feasibility of partial-RESET ML programming, 4 log-spaced levels within the available resistance window have been programmed by means of a staircase-up P&V algorithm.

Voltage Gain Analysis of Integrated Fibonacci-Like Charge Pumps for Low Power Applications

This paper presents an analysis of the achievable voltage gain in integrated Fibonacci-like charge pumps. The analysis is carried out by using a mathematical model based on a matrix description of the network which takes parasitic capacitances into account. The impact of top- and bottom-plate parasitics over the voltage gain is discussed and the analytical expression of the voltage gain as a function of parasitic capacitances is obtained. The derived set of equations is validated by means of circuit level simulations.

Intrinsic program instability in HfO2 RRAM and consequences on program algorithms

We statistically investigated for the first time resistance stability in HfO2 RRAM devices in the short (μs to s) transient after switching. We show that, the resistance value of both logic states is not stable after programming and subject to large discrete stochastic fluctuations. The frequency of fluctuation is found to be time-decaying thus hindering its detection in DC condition but considerably affecting throughput and effectiveness of write algorithms. We finally identify this instability as the primary source of the well-known resistance variability and we qualitatively explain it in terms of relaxation oscillation of filament microscopic configuration.

Experimental Analysis of Partial-SET State Stability in Phase-Change Memories

A key issue in nonvolatile storage is long-term data retention. This aspect is even more important in innovative storage technologies such as phase-change memory (PCM), which promises better performance and easier scalability with respect to traditional Flash memory and potential for multilevel storage. In this respect, we experimentally investigated the stability of intermediate states obtained by means of partial-SET programming. To this end, we analyzed the effects of the width and the amplitude of the programming pulses on the degradation of intermediate programmed resistance levels over time in PCM cells. Our study was carried out by considering the average behavior of an array of PCM cells, showing that data-retention properties degrade as the programming thermal stress increases.