Alessandro Cremonesi

A 100-MHz CMOS DAC for video-graphic systems

A 6-b weighted-current-sink video digital-to-analog converter (DAC) with 10-90% rise/fall time of 4 ns, integrated with a double-metal 3- mu m CMOS technology, is described. Current-source matching, glitch reduction, and differential switch driving aspects are considered. A circuit solution and a nonconventional layout technique yield a high conversion rate with a standard CMOS technology. Experimental results show that a conversion rate of 100 MHz is achievable. The power consumption is 150 mW and the active chip area is 0.5*1.0 mm/sup 2/. The differential of 0.1 LSB demonstrates that 8 b of accuracy can be achieved. The integral linearity is 0.5 LSB. >

An 8-bit two-step flash A/D converter for video applications

A novel configuration for two-step analog-to-digital (A/D) flash conversion is described. The coarse and fine conversions are performed with a four-bit multiplexed flash converter, so only 15 comparators are necessary for an eight-bit converter. The D/A conversion and the subtraction required for the circuit operation are performed using the charge redistribution technique. A test chip, integrated with a 3-μm CMOS technology (area=3 mm2), has demonstrated the effectiveness of the proposed configuration

A highly integrated processor for improved quality television

The paper presents the improved quality television IC, providing a superior TV image quality through noise reduction, scanning rate and format conversion, and picture enhancement. The device is implemented in 0.7 /spl mu/m CMOS technology, following a mixed design approach. >

Computing and design for software and silicon manufacturing

An increasing demand for higher performance, for lower power density, and for greatly expanded functionalities will determine radical changes in the future computing architectures. These widely acknowledged emerging trends are however insufficient to address all the challenges introduced by advanced silicon nanometer technologies. It is well known that manufacturability for high yield, along with design productivity and predictability and system reconfigurability for reduced NRE costs and faster time-to-market, are major problems in gigascale SoC design. Therefore, only focusing the design efforts on performance, power consumption, and throughput can hinder the potentials of the new computing architectures and limit the silicon yield. In this paper, we introduce an innovative architecture-to-silicon platform that by exploiting the concept of regularity at different levels of abstraction addresses the emerging challenges for the new computing architectures, and links system and architecture definition with silicon fabrication.

A highly integrated scanning rate converter for IQTV

The paper describes the multipurpose scanning rate converter (MSRC) IC, which improves TV image quality applying advanced scanning rate and format conversion techniques. The device has been designed to be inserted in an IQTV receiver to remove interlaced scan-related artifacts. The MSRC has been integrated using the 0.7 um CMOS technology, following a mixed custom/semicustom design approach. >

Multipurpose scanning rate converter IC for improved quality television

This paper describes a multistandard, highly integrated circuit, the Multipurpose Scanning Rate Converter (MSRC), implementing either the Field Rate Upconversion or the Interlaced-to-Progressive Conversion. Moreover, it applies Format Conversion techniques to display without distortions (4:3) images on a (16:9) screen. The MSRC IC follows a mixed custom/semicustom design approach, since custom line memories and DACs are inserted in a semicustom synthesis-generated circuit. The MSRC has been integrated using the 0.7 /spl mu/m CMOS technology and occupies an area of 53 mm/sup 2/.<<ETX>>

Video Deghosting Using Adaptive Echo-detecting I.I.R. Filters

This paper describes a novel adaptive channel equalizer (ACE), designed within the frame of the Europroject JESSI AE45B IQTV. According to an architectural indirect approach, the defined deghosting algorithm updates adaptively the system filter coefficients, to minimize the difference between the actual system output and the desired output signal. Thanks to an IIR filtering structure and to a novel deghosting algorithm, one is able to decrease effectively the filter coefficients, the system hardware complexity is reduced compared to the classic echo cancelling solutions. This feature makes ACE attractive for a single-chip VLSI implementation. >

Semiconductor Industry: Perspective, Evolution and Challenges

In this talk the major challenges that the semiconductor industry will have to face in the second decade of the new millennium will be addressed. The industry ecosystem is moving toward a new equilibrium and, in this context, the semiconductor Industry will continue to play a dominant role to fuel the growth in particular in the electronic field. New applications have a common denominator of growing complexity with more and more limited power and not only in the mobile space, this will push the industry to keep particular emphasis on the power budget of the new designs both at silicon and at system level. From the architecture stand point, multiprocessing is already a reality and the industry will have to find new paradigms to handle the increased complexity both at system, design & silicon implementation level. The interconnect, in particular, will assume a dominant role in the new SOC design, including 3D, becoming a more and more strategic resource to properly achieve the future design objectives.

General purpose video processor for high speed filtering applications

A video processor that allows the implementation of high-speed finite impulse response (FIR) video filters is described. This is made possible by using a parallel architecture implemented on 1.2 mu m CMOS EPROM technology. This solution makes it possible to overcome classical DSP (digital signal processing) problems such as processing speed, number of taps, flexibility, and volatility. The maximum achievable throughput in a single-chip configuration is 30 Mwords/s; such a processing speed allows comfortable use of the chip in the field of Rec. 601 (13.5 MHz sampling rate) while, in the case of HDTV (high-definition television), multiple-chip architectures may be configured to obtain a higher sampling rate. >