Alessandro Fantechi

Verifying hardware components within JACK

JACK (the acronym for Just Another Concurrency Kit) is a workbench integrating a set of verification tools for concurrent system specifications, supported by a graphical interface offering facilities to use these tools separately or in combination. The environment offers several functionalities to support the design, analysis and verification of systems specified using process algebras. In this paper we use JACK to formally specify the hardware components of a buffer system. Then we verify, by using the checking capabilities of JACK, the correctness of the specification with respect to some safety requirements, expressed in the action based temporal logic ACTL.

Formal Reasoning on Fault Coverage of Fault Tolerant Techniques: A Case Study

In this paper we show how a formal reasoning can be applied for studying the fault coverage of a fault tolerant technique when the behaviour of a system with a set of predefined faults is considered. This method is based on process algebras and equivalence theory. The behaviour of the system in absence of faults is formally specified and faults are assumed as random events which interfere with the system by modifying its behaviour. A fault tolerant technique can be proved to tolerate the set of predefined faults iff the actual behaviour of the system is the same as the behaviour of the system in absence of faults. The approach is illustrated by considering the design of a stable storage disk.

Formal Verification of Safety Requirements on Complex Systems

In this paper we present a logical characterization, by means of ACTL formulae, of safety requirements to be formally verified over safety critical complex systems. In this class of systems the formal verification of requirements is often hardened by state explosion problems. To deal with this problem, the characterization we propose allows the satisfiability of a safety requirement over a complex system to be derived by its satisfiability over those component subsystems that are directly involved in the given requirement. The proposed methodology has been successfully used for the formal verification of safety requirements of a particular system, that is a railway computer based signalling control system.

Tableau methods to describe strong bisimilarity on LOTOS processes involving pure interleaving and enabling

Several methodologies and most automatic tool support for LOTOS [1] can only be used if the specifications considered describe finite-state machines [2,3,4]. For example, an equivalence verifier can only manipulate specifications in this class; an attempt to verify the equivalence of two non finite-state processes may not terminate with an answer. However, as it is known, LOTOS gives the possibility to describe also non finite-state systems. So it could be useful to provide methodologies and tools for verification on this class of systems. Indeed more powerful verification techniques have recently been exploited for non-finite state systems defined in other process algebras.

An Expressive Logic for Basic Process Algebra

In this paper we present a branching time temporal logic for Basic Process Algebra. This logic is an enrichment of the branching temporal logic CTL with a branching sequential composition operator, named chop branching. The logic so obtained is proved to be expressive with respect to the bisimulation semantics defined on BPAδ, rec terms, and is able to describe context-free properties of systems.