Alessandro Grossi

Impact of Intercell and Intracell Variability on Forming and Switching Parameters in RRAM Arrays

The intercell variability of the initial state and the impact of dc and pulse forming on intercell variability as well as on intracell variability in TiN/HfO2/Ti/TiN 1 transistor - 1 resistor (1T-1R) devices in 4-kb memory arrays were investigated. Nearly 78% of devices on particular arrays were dc formed with a wordline (WL) voltage VWL = 1.4 V and a bitline (BL) voltage VBL = 2.3 V, whereas 22% of devices were not formed due to the combined effect of the extrinsic process-induced intercell variability of the initial state and the intrinsic intercell variability after dc forming. Furthermore, pulse-induced forming with pulsewidths on the order of 10 μs (VWL = 1.4 V and VBL = 3.5 V) caused for 86% of devices a low-resistance state. Using a retry algorithm, we achieve 100% of formed devices. To assess and confirm the nature of the variability during forming operation and during cycling, the quantum point-contact model was considered. The modeling results demonstrate a relationship between the forming and the device performance. The cells requiring high energy for the forming operation, due to impurities in the HfO2 deposition during array processing, are those subject to poor switching performance, larger variability, and faster wear out. Devices formed by a pulse-retry algorithm show: 1) shorter endurance and 2) higher variability during cycling.

Statistical analysis of resistive switching characteristics in ReRAM test arrays

The design and the manufacturing of ReRAM test structures allow deeper insight in the performance of the FORMING, RESET, and SET operations at array level, providing details on the process induced variability of the technology, and on the potential sources of failures. Test structures allow also demonstrating the integration capability of the ReRAM technology using a CMOS-compatible process ramping up such non-volatile memory to a maturity level.

Electrical characterization of read window in reram arrays under different SET/RESET cycling conditions

In this work a SET/RESET investigation in cycling on ReRAM arrays has been performed, in order to find the most reliable SET/RESET operation conditions. The analysis will compare DC and pulsed SET/RESET operations featuring different durations and voltages on previously DC formed 1T-lR4kbits memory arrays. A thorough analysis of the ReRAM reliability joining the cell-to-cell variability analysis to that of cycling evaluations in complete arrays is addressed. A comparison between DC and Pulse SET/RESET in terms of switching yield, read window, device-to-device uniformity and bit error rate is reported. Finally, the impact of a temperature bake at 1250C on a cycled array is shown to study the temperature impact on the array variability.

Relationship among Current Fluctuations during Forming, Cell-To-Cell Variability and Reliability in RRAM Arrays

In this work, cells behavior during forming is monitored through an incremental pulse and verify algorithm on 4kbit RRAM arrays. This technique allows recognising different cell behaviors in terms of read-verify current oscillation: the impact of these oscillations on reliability and cell-to-cell variability has been investigated during 1k endurance cycles and 100k pulse stress under a variety of cycling conditions. Conductance histograms for the post-forming current reveal the nanosized nature of the filamentary paths across the dielectric film.

Quality-of-Service Implications of Enhanced Program Algorithms for Charge-Trapping NAND in Future Solid-State Drives

Three-dimensional nand memory devices based on charge trapping (CT) technology represent the most promising solution for hyperscaled solid-state drives (SSDs). However, the intrinsic low reliability offered by that storage medium leads to a high number of errors requiring an extensive use of complex error correction codes (ECCs) and advanced read algorithms such as read retry. This materializes in an overall reduction in the SSDs QoS. In order to limit the error number, enhanced program algorithms that are able to improve the reliability figures of CT memory devices have been introduced. In this paper, the impact of such program algorithms combined with read retry and the ECC is experimentally characterized on CT- nand arrays. The results are then exploited for cosimulations at the system level, assessing the reliability, performance, and QoS of future SSDs integrating CT-based memory devices.

Reliability investigation of T-RAM cells for DRAM applications

In this work, we present a reliability investigation of T-RAM cells, considering their read failure, data retention and endurance. Experimental results on decananometer devices reveal a successful cell operation solving the voltage trade-off for optimal performance on state-0 and state-1, whose origin is explained by clear pictures of the physical processes giving rise to read failure and limiting data retention. Moreover, endurance results appear very promising, with cell functionality preserved up to very high cycling doses.

Performance and reliability comparison of 1T-1R RRAM arrays with amorphous and polycrystalline HfO2

In this work, a comparison between 1T-1R RRAM 4kbits arrays manufactured either with amorphous or polycrystalline HfO2 in terms of performance, reliability, Set/Reset operations energy requirements, intra-cell and inter-cell variability during 10k Set/Reset cycles is reported. Polycrystalline array shows higher current ratio, lower switching voltages, lower power consumption, minor endurance degradation and higher overall yield than amorphous array. The drawbacks are represented by the higher Forming voltage, the larger read current distribution after Forming and the higher Reset voltage dispersion.

Experimental demonstration of short and long term synaptic plasticity using OxRAM multi k-bit arrays for reliable detection in highly noisy input data

In this paper, we propose a new circuit architecture and a reading/programming strategy to emulate both Short and Long Term Plasticity (STP, LTP) rules using non-volatile OxRAM cells. For the first time, we show how the intrinsic OxRAM device switching probability at ultra-low power can be exploited to implement STP as well as LTP learning rules. Moreover, we demonstrate the computational power that STP can provide for reliable signal detection in highly noisy input data. A Fully Connected Neural Network incorporating STP and LTP learning rules is used to demonstrate two applications: (i) visual pattern extraction and (ii) decoding of neural signals. A high accuracy is obtained even in presence of significant background noise in the input data.

Charge retention phenomena in CT silicon nitride: Impact of technology and operating conditions

The aim of this work is to understand charge loss mechanisms in TANOS stack for which charge retention is monitored just after programming in an almost continuous way and voltage is applied during retention experiments in order to obtain zero electric field either on alumina or tunnel oxide. The charge loss mechanisms in TANOS stack can be a quite complicated process: An initial fast DT from interface traps localized at SiN/alumina interface, followed by charge loss through alumina from bulk traps in SiN which influences charge redistribution towards the tunnel oxide, observed only in Si-rich SiN. Programming voltage and stack composition impact trapped charge localization and hence charge redistribution and charge loss, even if the same initial Vfb is considered in charge retention experiments. While the charge loss through tunnel oxide is a DT, the charge loss through alumina depends on temperature and it is the main component of the charge loss in retention experiments for longer time.

Automated characterization of TAS-MRAM test arrays

In this work the characterization results of 1kbit TAS-MRAM arrays obtained through RIFLE Automated Test Equipment of 1Kbit array are reported. Such ATE, ensuring flexibility in terms of signals and timing, allowed evaluating hysteresis and to perform 50k write cycles in a very limited time, getting a first insight on TAS-MRAM arrays performance and reliability.