Alessandro Marras

Device simulations of silicon detectors: a design perspective

Device simulation allows for accurate analysis of device behavior, accounting for several physical details that cannot easily be taken into account within compact, equivalent-circuit models. This is especially true for some issues typical of the design of silicon radiation detectors, where silicon properties are exploited in a non-conventional way and radiation damage raises severe reliability concerns. In this paper, a couple of significant applications of device simulation to the investigation and design of advanced solid-state radiation sensors are presented. More specifically, (i) radiation damage influence on detectors operating at cryogenic temperatures is successfully modeled and (ii) features of an innovative scheme for CMOS active pixel sensors are analyzed by means of mixed-mode simulation tools. From these examples, the usefulness and potentiality of advanced simulation techniques in the perspective of radiation detectors can be appreciated.

Advanced active pixel architectures in standard CMOS technology

This paper aims at exploring and validating the adoption of standard fabrication processes for the realization of CMOS active pixel sensors, for particle detection purposes. The goal is to implement a single-chip, complete radiation sensor system, including on a CMOS integrated circuit the sensitive devices, read-out and signal processing circuits. A prototype chip (RAPS01) based on these principles has been already fabricated, and a chip characterization has been carried out; in particular, the evaluation of the sensitivity of the sensor response on the actual operating conditions was estimated, as well as the response uniformity. Optimization and tailoring of the sensor structures for High Energy Physics applications are being evaluated in the design of the next generation chip (RAPS02). Basic features of the new chip includes digitally configurable readout and multi-mode access (i.e., either sparse of line-scan readout).

3D monolithically stacked CMOS active pixel sensor detectors for particle tracking applications

In this work we propose an innovative approach to particle tracking based on CMOS Active Pixel Sensors layers, monolithically integrated in an all-in-one chip featuring multiple, stacked, fully functional detector layers capable to provide momentum measurement (particle impact point and direction) within a single detector. This will results in a very low material detector, thus dramatically reducing multiple scattering issues. To this purpose, we rely on the capabilities of the CMOS vertical scale integration (3D IC) technology. A first chip prototype has been fabricated within a multi-project run using a 130 nm CMOS Chartered/Tezzaron technology, featuring two layers bonded face-to-face. Tests have been carried out on full 3D structures, providing the functionalities of both tiers. To this purpose, laser scans have been carried out using highly focussed spot size obtaining coincidence responses of the two layers. Tests have been made as well with X-ray sources in order to calibrate the response of the sensor. Encouraging results have been found, fostering the suitability of both the adopted 3D-IC vertical scale fabrication technology and the proposed approach for particle tracking applications.

Tilted CMOS active pixel sensors for particle track reconstruction

In this work, we propose an innovative approach to characterize CMOS Active Pixel Sensors to be used for particle track reconstruction. The main idea is to use three pixel layers in the conventional way (e.g. orthogonally disposed with respect to the particle trajectory), whereas a fourth layer can be tilted with respect to the others up to 90 degrees. This would potentially allow for a better track reconstruction, thanks to the big number of reconstruction points. In order to check the suitability of the approach a dedicated tracking system featuring four sensors of 256×256 pixels has been assembled and tested at the INFN BTF, Frascati (Italy). Test results demonstrate the suitability of the approach, e.g. the system sensitivity to tilted trajectories.

Radiation Detectors for HEP Applications Using Standard CMOS Technology

The suitability of standard CMOS technology featuring no epitaxial layer for particle detection has been investigated through extensive experimental characterization. Different pixel layout and read-out schemes have been devised and implemented, as well as different test strategies. In this work test results are reported concerning the response of the detector to IR laser, beta-particles and X-rays stimuli, thus confirming the suitability of the proposed approach for high energy physics applications.

Advances in radiation active pixel sensors (RAPS) architectures

This work aims at exploring and validating the adoption of standard fabrication processes for the realization of CMOS active pixel sensor, for particle detection purposes. The goal is to implement a single-chip, complete radiation sensor system, including on a CMOS IC the sensitive devices, read-out and signal processing circuits. The possibility of including versatile and performing circuitry allows for the evaluation of innovative active pixel architectures, different read-out strategies, and complex data management algorithms. A prototype chip (RAPS01) based on these principles has been already fabricated, and a complete chip characterization has been carried out; in particular, the evaluation of the sensitivity of the sensor response on the actual operating conditions was estimated, as well as uniformity response analysis. Optimization and tailoring of the sensor structures for specific applications are being evaluated in the design of the next generation chip (RAPS02). In particular, sparse read-out approach and power consumption are considered, introducing some circuit improvement, and discussing the organization and design of a new architecture. Basic features of the new chip includes: digitally configurable readout, power-switching techniques, fault-tolerant circuitry, multi-mode access (i.e., either sparse of line-scan readout). Thanks to the intrinsic flexibility of CMOS design, perspective application different from HEP experiments, can be evaluated as well.

A two-tier monolithically stacked CMOS Active Pixel Sensor to measure charged particle direction

In this work we present an innovative approach to particle tracking based on CMOS Active Pixel Sensors (APS) layers, monolithically integrated in an all-in-one chip featuring multiple, stacked, fully functional detector layers capable to provide momentum measurement (particle direction) within a single detector by using multiple layer impact point coordinates. The whole system will results in a very low material detector, since each layer can be thinned down to tens of micrometres, thus dramatically reducing multiple scattering issues. To build such a detector, we rely on the capabilities of the CMOS vertical scale integration (3D-IC) 130 nm Chartered/Tezzaron technology, used to integrate two fully-functional CMOS APS matrix detectors, including both sensing area and control/signal elaboration circuitry, stacked in a monolithic device by means of Through Silicon Via (TSV) connections. Such a detector would allow accurate estimation of the impact point of an ionizing particle and of its incidence angle. Two batches of the first chip prototype have been produced and characterized using particle beams (e.g. protons) demonstrating the suitability of particle direction measurement with a single, multiple layers, 3D vertically stacked APS CMOS detector.

Design and test of innovative CMOS pixel detectors

Abstract In this work, design, implementation and test phases of a radiation sensor based on active pixel architectures are discussed. Fully standard CMOS technology has been exploited, allowing for easier integration of signal-processing circuitry. Alternative circuit schemes have been considered; a novel architecture, called WIPS, is introduced, aimed at a more efficient sparse-access mode of the sensor array. A first prototype of the chip has been fabricated, in a 0.18 μ m CMOS technology. An automatic testing procedure has been devised, including design and fabrication of a suitable test board and of an optical bench. Preliminary results of the measurements are given, validating the overall approach and the operating principle of the WIPS architecture.