Alex Cognata

Linearity characteristics of GaAs HBTs and the influence of collector design

The linearity characteristics of GaAs heterojunction bipolar transistors (HBTs) are studied through measurement and analysis. Third-order intermodulation distortion behavior of HBTs is examined on devices with various epilayer designs and at various bias points, loads, and frequencies. Calculations from an analytical model reveal a strong bias and load dependence of third-order intercept point (IP3) on the nonlinearities from transconductance and the voltage dependence of base-collector capacitance. However, a simple model is not able to predict the fine details of IP3 with bias. A large-signal HBT model with an accurate description of the base-collector charge is shown to account for the measured trends. The base-collector charge function accounts for the modulation of base-collector capacitance with current, electron velocity modulation, and the Kirk effect (base pushout) for GaAs-based HBTs. A detailed study of the influence of collector design on linearity is also presented.

Large-signal HBT model with improved collector transit time formulation for GaAs and InP technologies

An analytical large-signal HBT model which accurately accounts for the intricate bias dependence of collector delay in devices fabricated in both GaAs and InP material systems is described. The strongly bias dependent collector delay function accounts for the variation of electron velocity with electric field of the collector, which has consequences for both the electron transit time and capacitance. It is shown that the new formulation significantly improves the prediction of the bias dependence of f/sub t/. As a result, simulations over a very wide range of operating conditions match measured data on a wide variety of devices. Distortion predictions are improved since the derivatives of the bias dependent delay are more accurately modeled. This new model is extracted on medium and high breakdown GaAs HBTs, and also on InP DHBTs. Simulation results are verified with comparisons to S-parameter and large-signal measurements.

Multi-tone, Multi-port, and Dynamic Memory Enhancements to PHD Nonlinear Behavioral Models from Large-signal Measurements and Simulations

The PHD nonlinear behavioral model is extended to handle multiple large tones at an arbitrary number of ports, and enhanced for dynamic long-term memory. New capabilities are exemplified by an amplifier model, derived from large-signal network analyzer (LSNA) data, valid for arbitrary impedance environments, and a model of a 50GHz integrated mixer, including leakage terms and IF mismatch dependence. Dynamic memory is demonstrated by an HBT amplifier model identified from up-converted band-limited noise excitations. The models are validated with independent LSNA component data or, for simulation-based models, with the corresponding circuit models.

Enhanced on-wafer time-domain waveform measurement through removal of interconnect dispersion and measurement instrument jitter

We measure output waveshape and rise time of two high-speed digital circuits on wafer using a 50-GHz prototype of a new instrument. The instrument uses vector error correction to deembed the component under test like a network analyzer, but reads out in the time domain after the fashion of an equivalent-time oscilloscope. With the calibration plane of the instrument set at the tips of the wafer probes, errors arising from dispersion in the con- nection hardware are removed. We show that the random jitter in the measurement system is removed without the convolution penalty usually incurred by averaging so that anomalies such as pattern-dependent jitter are exposed. The system rise time is 7 ps, compared to a system rise time of 12-13 ps for a conventional equivalent-time oscilloscope of the same bandwidth in the presence of wafer probes, bias networks, and cables.

Drain-Source Symmetric Artificial Neural Network-Based FET Model with Robust Extrapolation Beyond Training Data

A large-signal FET model based on artificial neural networks (ANNs) is extended for rigorous intrinsic drain-source symmetry and robust extrapolation beyond the range of training data. Enhanced ANN architectures and training algorithms constrain the five nonlinear model state functions to transform according to the discrete symmetry rules related to the device invariance with respect to intrinsic drain-source exchange. This extends the applicability of the previous ANN-based model to situations where the instantaneous voltage crosses Vds= 0, such as switches and mixers. The model is compiled in Agilent ADS, together with advanced extrapolation routines extending the model beyond the range of training data for improved convergence. The model has been generated for FETs from several III-V semiconductor processes, and validated with extensive independent small and large-signal measurements.

Nonlinear microwave/RF system design and simulation using Agilent ADS 'system - data models'

The successful design of multi-chip modules for microwave systems using EDA tools has been enabled by using behavioral models for the IC components. Data-based models were created from large-signal measurements or simulations of the ICs, and the nonlinear performance of the module, such as gain compression, was simulated accurately.

A 0.5-50 GHz on-wafer, intermodulation, load-pull and power measurement system

A novel on-wafer, intermodulation, load-pull and power measurement system for characterizing devices and circuits for frequencies up to 50 GHz has been developed. The two-tone intermodulation measurement capabilities were added to an existing power and harmonic load-pull measurement system using the 50 GHz spectrum analyzer HP8565. Fundamental power levels and all measured intermodulation (IM) products are vector corrected to the probe tips of the DUT. A key feature of the described system are the vector corrected IM measurements and the capability to study the effects of load impedance on intermodulation.<<ETX>>

Removal of cable and connector dispersion in time-domain waveform measurements on 40 Gb integrated circuits

A new instrument for time-domain characterization of circuits is illustrated. We measure output waveshape and rise time of two high-speed digital circuits on wafer, using a 50 GHz prototype of the new instrument. It uses vector error-correction to de-embed the component under test like a network analyzer but reads out in the time-domain after the fashion of an equivalent-time oscilloscope. With the calibration plane of the instrument set at the tips of the wafer probes, errors arising from dispersion in the connection hardware are removed. A further benefit of this instrument is that random jitter is removed without the convolution penalty usually incurred by averaging, so that anomalies such as pattern dependent jitter are exposed. The system risetime is 7 ps, compared to a system risetime of 12-13 ps for a conventional equivalent-time oscilloscope of the same bandwidth in the presence of wafer probes, bias networks, and cables.