Alex Pw Lee

A design platform for analog device size sensitivity analysis and visualization

A symbolic calculation method for the sensitivity of frequency response to semiconductor device sizes is addressed for application in analog integrated circuit design. The transistor-size-based ac-sensitivity can be used for sizing devices and understanding the circuit behavior. Examples are provided to demonstrate that a design platform supported by symbolic ac-sensitivity and visualization can be a helpful tool for computer-aided design of analog integrated circuit.

Digital calibration technique for A 14-bit 125-MS/s pipelined ADC using PN dithering

This paper presents a new scheme of digital calibration for a 14-bit 125-MS/s pipelined ADC. The proposed digital calibration corrects the linearity errors resulted from capacitor mismatches, finite Operational Transconductance Amplifier (OTA) gain and OTAs settling error. This calibration method is based on radix-based calibration, and Pseudo-random Noise (PN) sequence is injected into the Multiplying DAC (MDAC) to extract the equivalent radix. According to the calibration system, simulation results show that when the prototype ADC is sampled at 125 MS/s, the Spurious Free Dynamic Range (SFDR) improves from 51.64 dB to 102.27 dB with calibration, and the Signal to Noise and Distortion Ratio (SNDR) improves from 36.47 dB to 80.86 dB with calibration.

LONGITUDINAL STRAIN ASSESSED BY 2D SPECKLE TRACKING ECHOCARDIOGRAPHY PREDICTS MICROVASCULAR OBSTRUCTION IN PATIENTS WITH ST ELEVATION MYOCARDIAL INFARCTION

Microvascular obstruction (MVO) following ST elevation myocardial infarction (STEMI) is associated with larger infarct size and an increased mortality. We hypothesized that longitudinal strain (LST) assessed by 2D speckle tracking echocardiography (2DSTE) could predict MVO after primary percutaneous

Radix-based digital calibration method for pipelined ADCs with signal-dependent dithering

This paper presents a new digital calibration method for a 14-bit 140MS/s pipelined analog-to-digital converter (ADC). Signal-dependent Pseudo-random Noise (PN) sequences are injected into the first 3.5-bit multiplying digital-to-analog converter (MDAC) without interrupting its normal conversion operation to extract the radix term, which includes finite opamp gain, settling error and capacitor mismatch. Compared to conventional fixed magnitude PN dithering, signal-dependent dithering greatly improves the signal-to-noise plus distortion (SNDR) of the ADC and reduces the calibration time. By using proposed method, the ADC achieves a peak SNDR of 81.5dB and spurious-free dynamic range (SFDR) of 102.8dB with 31.6MHz input at 140MS/s and the ENOB is improved from 6.5 bits to 13.25 bits.

An FPGA implemented 24-bit audio DAC with 1-bit sigma-delta modulator

This paper presents the design and FPGA implementation of a 24-bit audio DAC incorporating a set of multiplier-free interpolation filters and a 4th-order 1-bit sigma-delta modulator (SDM). The whole system achieves a signal to noise ratio (SNR) as high as 139dB with idle tones and noise modulation virtually eliminated. For the fixed point interpolation filters, multiplier-free canonical signed digits (CSD) coefficients are chosen to sharply reduce FPGA resources utilization. And the zeros of SDM are psychoacoustically optimized to minimize the total perceived output noise power so that the resultant noise within the signal band becomes unobjectionable to the human ear. Furthermore, in order to eliminate the idle tones notorious in 1-bit SDM, single-bit dither of ±0.125 amplitude is added while guaranteeing a maximum stable input range of −5.19dBFS.