Alexandre Siligaris

A 65-nm CMOS Fully Integrated Transceiver Module for 60-GHz Wireless HD Applications

This paper presents a fully integrated 60GHz transceiver module in a 65nm CMOS technology for wireless high-definition video streaming. The CMOS chip is compatible with the WirelessHD™ standard, covers the four channels and supports 16-QAM OFDM signals including the analog baseband. The ESD-protected die (9.3mm²) is flip-chipped atop a High Temperature Cofired Ceramic (HTCC) substrate, which receives also an external PA and the emission and reception glass-substrate antennas. The module occupies an area of only 13.5×8.5mm². It consumes 454mW in receiver mode and 1.357W in transmitter mode (357mW for the transmitter and 1W for the PA).

A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI

A 60 GHz wideband power amplifier (PA) is fabricated in a standard CMOS SOI 65 nm process. The PA is based on two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high-resistivity SOI substrate (3 kΩ · cm). The PA measurements are carried out for supply voltages VDD going from 1.2 V to 2.6 V and achieve a saturation power of 10 dBm to 16.5 dBm respectively. The peak power-added efficiency (PAE) is higher than 20% for all applied VDD values.

A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications

This work shows a complete PLL that is integrated in standard industrial 65nm CMOS technology. This frequency synthesizer is fully compliant with IEEE 802.15.3c normalization [1–4]. This PLL delivers a quadrature LO signal around 20GHz and a differential LO signal around 40GHz and has 17.9% tuning range. The wide tuning range of 17.9% permits to cover the full IEEE 802.15.3c band with industrial margin. The phase noise is −100dBc/Hz at 1MHz offset and the total power dissipation is only 80mW including the output buffers and amplifiers. Short-range wireless multi-Gb/sec communication systems use the mm-wave band of 57GHz to 66GHz, according to the IEEE 802.15.3c normalization. The frequency synthesis is one of the key elements for these transceivers. Indeed, one must take into account the antagonist tradeoff between large band tuning range of the frequency synthesizer and phase noise performance. In transceivers using super-heterodyne architecture with double conversion, the frequency synthesizer signal fLO can be equal to 2fRF /3 and fRF /3. In this case, to cover the four channels of the IEEE 802.15.3c normalization, the frequency synthesizer has to deliver a first local oscillator (LO) signal between 19.44GHz and 21.6GHz and a second LO signal between 38.88GHz and 43.2GHz, respectively. This architecture offers a good trade off between the required large frequency tuning range (≫15%) and low phase noise (≪−95dBc/Hz).

A 53-to-68GHz 18dBm power amplifier with an 8-way combiner in standard 65nm CMOS

CMOS circuits operating up to 60GHz have been demonstrated to satisfy the market demand for high data rates and frequency bandwidths [1–6]. However, 60GHz products need an improvement in power performance as well as transistor reliability for large signal operation. Moreover, Class-A or Class-AB power amplifiers (PA) are mandatory to overcome the difficulty of the limited maximum available gain (MAG) at mm-Wave frequencies [1–6] and the high linearity required by the OFDM modulation used in the IEEE 802.15.3c wireless HD standard. That means a maximum drain-source voltage swing of twice the DC voltage, which introduces specific design or supply voltage in order to respect reliability constraints [1,7]. This paper describes a PA with 8 power-combined ways and cascode topology in a 7-metal-layer 65nm CMOS process which covers the full band for 60GHz wireless applications. The presented circuit operates at a standard supply of 1.2V or 1.8V, and achieves a saturated output power of 16.6dBm and 18.1dBm respectively. The measured output power is high for CMOS while insuring reliability for time-dependent dielectric breakdown (TDDB) and hot-carrier-injection (HCI) degradation.

A 60GHz power amplifier with 14.5dBm saturation power and 25% peak PAE in CMOS 65nm SOI

A 60GHz wideband power amplifier (PA) is fabricated in standard CMOS SOI 65nm process. The PA is constituted by two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high resistivity SOI substrate. The PA measurements are carried out for supply voltages VDD going from 1.2V to 2.6V and achieve a saturation power of 10dBm to 16.5dBm respectively. The peak power added efficiency is higher than 20% for all applied VDD values.

Ultra low consumption UWB pulsed-ILO RF front-end transmitter at 60 GHz in 65-nm CMOS-SOI

A super high order sub-harmonic pulsed-ILO at 60 GHz in 65-nm CMOS-SOI has been fully designed and tested. It occupies 0.16 mm2 active area in 65-nm CMOS-SOI. Input digital locking signal modulates the oscillator at 60 GHz from ON to OFF state using a current source. Thus, the millimeter wave oscillation does not start from the thermal noise but from one of the numerous harmonic components of the pulse generator synthesized in the locking millimeter band. The theoretical 20log(N) increase phase noise has been verified measuring the output millimeter wave signal jitter and phase noise (-92 dBc/Hz at 100 KHz). As a consequence, a stable pulse to pulse phase condition is reached, making this sub-harmonic pulsed-ILO suitable for automobile radar, Giga-bit WLAN, Wireless Sensor Networks (WSN) and localization with an optimized consumption. Its peak power output is 5 dBm under a 1.4 V 16 mA bias. At OFF state, the dc current consumption is negligible. The equivalent sinus peak output power is 4 dBm, leading to a peak efficiency of 14%. As a consequence, the global efficiency of the RF front-end transmitter is less than 4 pJ/pulse.

A novel ultra-low phase noise, programmable frequency multiplier-by-30 architecture. Application to 60-GHz frequency generation

This paper presents an original mmW frequency multiplier that provides a 58.32 GHz to 62.64 GHz LO starting from a much lower and fixed frequency of 2.16 GHz. It is composed of a pulsed VCO, which generates equally spaced harmonics in the 60 GHz band, and an injection locked oscillator (ILO) that selects the harmonic of interest. The CMOS 40nm circuit consumes 32 mW and occupies only 0.07 mm2. This novel programmable multiplication technique requires a unique fixed low frequency reference to perform multi-channel mmW LO generation. The phase noise of the output LO signal is only limited by the input low frequency reference phase noise and the frequency ratio between output and input signals. Thus, a 60 GHz signal has been generated with this technique with a record phase noise of -104 dBc/Hz @ 1MHz offset.

On-chip/in-package integrated antenna for millimeter-wave medium and long-range applications

A novel cost-efficient antenna solution for millimeter-wave multi-Gbps wireless communications operating over ranges above 10-20 meters in fixed Line-Of-Sight (LOS) configuration is presented. A first antenna element is integrated on-chip with a CMOS-SOI 60-GHz transceiver circuit in order to benefit from minimum interconnection losses between the front-end circuit and the antenna. This antenna is coupled to an external radiating element embedded in a standard QFN package, enabling an improved radiation gain of 4-6 dBi. Finally, a discrete-lens antenna array fabricated on standard laminate materials is placed above the packaged transceiver in order to focus the radiated beam and reach a gain in excess of 14 dBi.