Alexis Landrault

A MP-SoC design methodology for the fast prototyping of embedded image processing system

This article proposes an original design flow for the fast prototyping of image processing on a MP-SoC (MultiProcessors System on Chip) architecture. Developing processors network systems tailored to a particular application domain is critical and design-time consuming in order to achieve highperformance customized solutions. The effectiveness of such approaches largely depends on the availability of an ad hoc design methodology. This paper illustrates a new design flow that enables to instantiate a generic Homogeneous Network of Communicating Processors (called HNCP) tailored for a targeted application. The HNCP is generated with a tool that avoids fastidious manual editing operations for the designer. Specific lightweight communication functions have been developed to fasten the programming of the MP-SoC network. A case study (image texture analyzes) is presented to illustrate the proposed MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.

Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

Highly regular multi-processor architectures are suitable for inherently highly parallelizable applications such as most of the image processing domain. Systems embedded in a single programmable chip platform (SoPC) allow hardware designers to tailor every aspect of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of cores, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on a SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirements and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs (Intellectual Property). We present both software and hardware implementation with performance results on a Xilinx SoPC target.

Embedded multi-processor system-on-programmable chip for smart camera pose estimation using nonlinear optimization methods

The PanoraMOS prototype is a complete localization system targeting Simultaneous Localization and Mapping applications. It is a panoramic camera that uses a single rotating linear sensor to capture cylindrical panoramic images at up to 3 frames per second. A complete localization algorithm has been implemented into the hardware architecture of the system. It has the ability to estimate its 3D pose in an indoor or an outdoor environment. This estimation is performed using a feature extractor and the Levenberg–Marquardt (LM) algorithm with the Random Sample Consensus (RANSAC) algorithm to perform detection. In this paper, we present the whole system particularly emphasize the localization algorithm and its implementation on a hardware architecture which is our main contribution. The implementation was done on a Multi-Processor System-on-Chip architecture. We present both software and hardware implementations with performance results on an ALTERA System-on-Programmable Chip target. The experimental results including processing times and application speed up show that our homogeneous network of processors is efficient for embedding the proposed image processing application.

A novel flexible 16-core MP-SoC architecture based on parallel skeletons for image processing applications

For many image processing systems, the computing power required can not be provided by a single sequential processor, this is why many designers appeal to multiprocessor systems (parallelism). This article proposes an original flexible MP-SoC (Multi-Processors System on Chip) architecture for image processing applications. Developing processors network systems tailored to a particular application domain is critical and design-time consuming in order to achieve high-performance customized solutions. This paper introduces a 16-core MP-SoC ASIC with a software configuration. In particular, each tile of the network can configure its communication links depending on the most relevant overall parallelism scheme for a targeted application. Results are shown in term of power, area and timing performance for a 65 nm CMOS technology ASIC design. A case study (grey scale histogram analyzes) is presented to illustrate the proposed flexible MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.

A generic packet router IP for multi-processors network-on-chip

In this paper, a generic IP is proposed to ensure communication for a Multi-Processors System on Chip (MPSoC) architecture. It is based on a specific hardware router and its associated Direct Memory Access (DMA) module. This scalable IP makes the instantiation easier and faster in MPSoC systems based on hypercube topology. Besides the hardware description, this work also presents the software layer and the communication functions developed to help the parallel programming based on functional skeletons. Implementation results are given regarding processing time, area and processor number on a Virtex 6 Xilinx FPGA target.

Embedding of a Real Time Image Stabilization Algorithm on SoPC Platform, a Chip Multi-processor Approach

Highly regular multi-processor architecture are suitable for inherently highly parallelizable applications such as most of the image processing domain. System on a programmable chip (SoPC) allows hardware designers to tailor every aspects of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of core, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirement and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs. We present both software and hardware implementation with performance results on a Xilinx SoPC target.

A control unit module for a scalable floating-point-unit architecture

The gap of execution time between software and hardware computing is significant and becomes more and more important when precision is required as it is the case for the floating point calculation. This paper presents the addition of a Floating Point Unit (FPU) module to an open-source processor called SecretBlaze. Besides the description of the chosen processor enhanced by FPU thanks to user instructions, this work focuses on the hardware method to add the scalable FPU system. As a first step, design implementations enable to compare chosen FPU with other FPU available in the open-source community. It also enables to evaluate the performance of the FPU added to the processor. As a second step, we present an FPU control unit added to the architecture in order to realize several functions with few resources. All proposed architectures have been implemented and tested on FPGA target.

HNCP-II: A 16-core 65nm microprocessor ASIC for image processing algorithms

In many video and image processing applications, complexity has reached a point where the performance requirements can no longer be supported by standard architectures based on a single processor. This is why many systems are based on multiprocessor architecture. In this paper, we present HNCP-II a 16-core flexible distributed memory ASIC dedicated to embedded application field (image processing applications). Connected through a torus on-chip network, each tile of the overall system includes an open-source RISC processor, a floating point unit, a video management module and a set of built in hardware features for multicore communication. This specific hardware enables to meet most relevant overall parallelism scheme (parallel skeletons) thanks to software-configurable modules. Results are presented for two image processing algorithms in term of execution time, speedup and efficiency. Area, power and timing performance of the synthesized ASIC are given for a CMOS 65nm technology node.

Teaching advanced digital ASIC designs by a complex case study

Many previous works have introduced courses on necessary design steps for a basic knowledge of the digital ASIC design flow. This paper intends to introduce a series of labs focusing on ASIC design flow on a complex case study. Indeed, many difficult aspects of the ASIC flow only appear with complex design. This course enables teaching modern and industrial advanced digital ASIC design methodologies in a university environment with a deep-submicron technology node (CMOS 65nm from ST-microelectronics). As a result of this gradual and coherent training, students gain skills that allow them to undertake large and complex ASIC design project.

A generic MP-SoC design methodology for the fast prototyping of embedded image processing

This article proposes an original methodology for the fast prototyping of image processing on a generic MP-SoC (Multi-Processors System on Chip) architecture. To define a processors network adapted to a particular application is critical and design-time consuming in order to achieve high-performance customized solutions. The effectiveness of such approaches largely depends on the availability of an ad hoc design methodology. This paper illustrates a new methodology that enables to instantiate a generic Homogeneous Network of Communicating Processors (called HNCP) tailored for a targeted application. The HNCP is generated with a tool that avoids fastidious manual editing operations for the designer. Specific lightweight communication functions have been developed to fasten the programming of the MP-SoC network. A case study (image texture analyzes) is presented to illustrate the proposed MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.