Alfio Zanchi

A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter

The analog-to-digital converter presented in this work demonstrates the efficiency of the straight 2.5 bit-per-stage approach for the implementation of pipelined switched-capacitor architectures targeting up to 16-bit resolution and 65-MS/s sampling rate. The test chip has been fabricated in a 45-GHz f/sub T/, 0.4-/spl mu/m 3.3-V SiGe BiCMOS process that makes it suitable for integration with an RF front-end toward an antenna-to-DSP communication processor. Performance of 78.3 dBFS SNR, 88dBc SFDR at 65 MS/s, 1 MHz input is obtained without trimming or calibration, dissipating 970 mW total with external references. Since the 4 V/sub p-p/ signal range chosen for high SNR could lead to distortion in the Sample/Hold and the pipelined quantizer with only 3.3-V supply, a fast and accurate SPICE simulation technique for INL investigation is described that enabled detailed diagnosis of potential nonlinearity sources. Theoretical analysis and practical implementation of the clock circuit are also discussed allowing the design of a CMOS-based clock featuring 180-fs jitter, which preserves high SNR against input frequency: state-of-the-art 73.5dBFS have been observed at 150 MHz input, popular intermediate frequency (IF) for single-heterodyne BTS receivers. Finally, the figures of merit encompassing power, effective resolution, and speed rank the dynamic performance of the ADC core among the best in its class.

Impact of capacitor dielectric relaxation on a 14-bit 70-MS/s pipeline ADC in 3-V BiCMOS

In this paper, phenomena of charge absorption and relaxation in the plasma enhanced chemical vapor deposition (PECVD) silicon nitride dielectric (Si/sub 3/N/sub 4/) used in the capacitors of a 45-GHz f/sub T/, 0.4-/spl mu/m L/sub min/ SiGe BiCMOS are observed and interpreted. When such capacitors are used to design a pipelined 14-bit 70-MS/s switched-capacitor analog-to-digital converter (ADC), dielectric relaxation is identified as the cause of 8-LSB-wide gaps in the integral nonlinearity, which leads to the degradation of the converter performance even at low frequencies. The effect has been analyzed via Matlab behavioral simulations and SPICE circuit simulations. Ad-hoc experimental tests aimed at detecting residual amounts of charge left in the capacitors as a memory of previous states have been also carried out. After low-density low-pressure chemical vapor deposition (LPCVD) oxide capacitors (SiO/sub 2/) are introduced in the process, a new ADC test chip delivers 72.5-dBFS SNR, 82-dBc SFDR, 11.7-bit ENOB at 70 MS/s and 1-MHz input. The circuit features a die size of 5.3 /spl times/ 5.3 mm/sup 2/ and dissipates 1 W from the 3.3-V supply.

Measurement and SPICE prediction of sub-picosecond clock jitter in A/D converters

We propose an innovative characterization technique that allows us to discriminate noise contributions due to jitter from other phenomena (voltage reference and substrate noise, high-amplitude effects) in A-to-D converters. The jitter estimated with this method closely matches that inferred from the signal-to-noise ratio at high input frequencies, where noise is dominated by the aperture uncertainty. At the sub-picosecond level required for the 14-b high-IF ADC under test, any off-chip disturbances substantially affect the accuracy of the measurement. In order to characterize the uncertainty, first the phase noise spectrum of the external clock source is measured and converted into jitter by way of a rigorous formula. Then, the timing ambiguity associated with the on-chip clock pre-amplification and distribution circuitry is simulated via standard Spice techniques, providing results in agreement with experimental evidence. The paper provides tools to isolate the main noise sources in the clock circuit, and optimize it for low jitter in the early simulation phase. Moreover, it arms the designer with a robust yet easy experimental method to assess the jitter value, and interpret the SNR data gathered from test silicon.

Impact of dielectric relaxation on a 14 b pipeline ADC in 3 V SiGe BiCMOS

Dielectric relaxation in PECVD SiN capacitors of a 45 GHz 0.4 /spl mu/m SiGe BiCMOS process degrades performance even at low frequencies. In the design of pipelined 14 b 70 MS/s ADC, the effects of dielectric relaxation are identified via behavioral/circuit simulations and ad-hoc tests. After LPCVD oxide capacitors are introduced, a 5.3/spl times/5.3 mm/sup 2/ test chip delivers 72 dB SNR, 81 dBc SFDR, and 11.5 ENOB at 70 MS/s with a 1 MHz input. The IC dissipates 1 W from 3.3 V.