Alfredo Cristóbal-Salas

Non-strict execution in parallel and distributed computing

This paper surveys and demonstrates the power of non-strict evaluation in applications executed on distributed architectures. We present the design, implementation, and experimental evaluation of single assignment, incomplete data structures in a distributed memory architecture and Abstract Network Machine (ANM). Incremental Structures (IS), Incremental Structure Software Cache (ISSC), and Dynamic Incremental Structures (DIS) provide non-strict data access and fully asynchronous operations that make them highly suited for the exploitation of fine-grain parallelism in distributed memory systems. We focus on split-phase memory operations and non-strict information processing under a distributed address space to improve the overall system performance. A novel technique of optimization at the communication level is proposed and described. We use partial evaluation of local and remote memory accesses not only to remove much of the excess overhead of message passing, but also to reduce the number of messages when some information about the input or part of the input is known. We show that split-phase transactions of IS, together with the ability of deferring reads, allow partial evaluation of distributed programs without losing determinacy. Our experimental evaluation indicates that commodity PC clusters with both IS and a caching mechanism, ISSC, are more robust. The system can deliver speedup for both regular and irregular applications. We also show that partial evaluation of memory accesses decreases the traffic in the interconnection network and improves the performance of MPI IS and MPI ISSC applications.

Using Tree Diagram Concepts to model Use Case Flows

The level and quality of the abstraction applied during the analysis phase are key factors for the product robustness and project success. There are not so much techniques to organize the abstraction performed. Also, in the software development process, the analysis phase suffers of a lack of formality at the level of the use cases analysis and description. In this paper we present an approach based on the analogy between probabilistic sequential events and the steps of a use case flow. This analogy represents a kind of formalization that supports the use case flows characterization. Using this approach, the use cases analysis can be performed in a methodological way supported by formal fundamentals.

A Methodology for Use Cases Modeling Based on Sequence Diagrams Quantification

In this paper we describe a methodology to model a use case using sequence diagrams quantification. Our methodology consists in a set of metrics to define the amount of scenarios, and it determines the use case goal accomplishment based on the occurrence, sequence order, and the flow of data involved in. It also helps to obtain a robust design because all possible flows are considered; by this way, software quality could be achieved in quantitative terms. This approach can be used in two ways: to define a complete set of scenarios before entering in the design phase, and to measure design quality in terms of completeness and functionality attributes. Our methodology follows the main recommendations to apply a solid mathematical basis for engineering careers, and informatics and computing programs.

Exploiting single-assignment properties to optimize message-passing programs by code transformations

The message-passing paradigm is now widely accepted and used mainly for inter-process communication in distributed memory parallel systems. However, one of its disadvantages is the high cost associated with the data exchange. Therefore, in this paper, we describe a message-passing optimization technique based on the exploitation of single-assignment and constant information properties to reduce the number of communications. Similar to the more general partial evaluation approach, technique evaluates local and remote memory operations when only part of the input is known or available; it further specializes the program with respect to the input data. It is applied to the programs, which use a distributed single-assignment memory system. Experimental results show a considerable speedup in programs running in computer systems with slow interconnection networks. We also show that single assignment memory systems can have better network latency tolerance and the overhead introduced by its management can be hidden.

Non-strict Evaluation of the FFT Algorithm in Distributed Memory Systems

This paper focuses on the partial evaluation of local and remote memory accesses of distributed applications, not only to remove much of the excess overhead of message passing implementations, but also to reduce the number of messages, when some information about the input data set is known. The use of split- phase memory operations, the exploitation of spatial data locality, and non-strict information processing are described. Through a detailed performance analysis, we establish conditions under which the technique is beneficial. We show that by incorporating non-strict information processing to FFT MPI, a significant reduction of the number of messages can be archived, and the overall system performance can be improved.

INTRODUCING THE EXTREMELY HETEROGENEOUS ARCHITECTURE

The computer industry is moving towards two extremes: extremely high-performance high-throughput cloud computing, and low-power mobile computing. Cloud computing, while providing high performance, is very costly. Google and Microsoft Bing spend billions of dollars each year to maintain their server farms, mainly due to the high power bills. On the other hand, mobile computing is under a very tight energy budget, but yet the end users demand ever increasing performance on these devices. This trend indicates that conventional architectures are not able to deliver high-performance and low power consumption at the same time, and we need a new architecture model to address the needs of both extremes. In this paper, we thus introduce our Extremely Heterogeneous Architecture (EHA) project: EHA is a novel architecture that incorporates both general-purpose and specialized cores on the same chip. The general-purpose cores take care of generic control and computation. On the other hand, the specialized cores, including GPU, hard accelerators (ASIC accelerators), and soft accelerators (FPGAs), are designed for accelerating frequently used or heavy weight applications. When acceleration is not needed, the specialized cores are turned off to reduce power consumption. We demonstrate that EHA is able to improve performance through acceleration, and at the same time reduce power consumption. Since EHA is a heterogeneous architecture, it is suitable for accelerating heterogeneous workloads on the same chip. For example, data centers and clouds provide many services, including media streaming, searching, indexing, scientific computations. The ultimate goal of the EHA project is two-fold: first, to design a chip that is able to run different cloud services on it, and through this design, we would be able to greatly reduce the cost, both recurring and non-recurring, of data centers\clouds; second, to design a light-weight EHA that runs on mobile devices, providing end users with improved experience even under tight battery budget constraints.

Teaching undergraduate students to model use cases using tree diagram concepts

A new approach for use cases description is exposed. It is based on four mathematical concepts: sequential events, possible results, tree diagrams, and permutations. This approach pretends to encourage undergraduate students to use formal concepts in software engineering, in order to reduce the lack of formality that this discipline suffers.

Partial evaluation technique for distributed image processing

In this paper, a partial evaluation technique to reduce communication costs of distributed image processing is presented. It combines application of incomplete structures and partial evaluation together with classical program optimization such as constant-propagation, loop unrolling and dead-code elimination. Through a detailed performance analysis, we establish conditions under which the technique is beneficial.