Ali Manzak

Variable voltage task scheduling algorithms for minimizing energy/power

In this paper, we propose variable voltage task scheduling algorithms that minimize energy or minimize peak power for the case when the task arrival times, deadline times, execution times, periods, and switching activities are given. We consider aperiodic (earliest due date, earliest deadline first), as well as periodic (rate monotonic, earliest deadline first) scheduling algorithms. We use the Lagrange multiplier method to theoretically determine the relation between the task voltages such that the energy or peak power is minimum, and then develop an iterative algorithm that satisfies the relation. The asymptotic complexity of the existing scheduling algorithms change very mildly with the application of the proposed algorithms. We show experimentally (random experiments as well as real-life cases), that the voltage assignment obtained by the proposed low-complexity algorithm is very close to that of the optimal energy (0.1% error) and optimal peak power (1% error) assignment.

A low power scheduling scheme with resources operating at multiple voltages

This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V, 2.4 V, and 1.5 V). The proposed algorithms are based on efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy relation derived using the Lagrange multiplier method in an iterative fashion. Two algorithms are proposed, 1) a low complexity O(n/sup 2/) algorithm and 2) a high complexity O(n/sup 2/ log(L)) algorithm, where n is the number of nodes and L is the latency. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 1.5 times the critical path delay, the average reduction is 39%.

Variable voltage task scheduling for minimizing energy or minimizing power

We propose task scheduling algorithms that minimize energy or minimize power for the case when the tasks have different arrival times, deadline times, execution times and switching activities. We theoretically determine the relation between the operating voltages for the minimum energy (power) assignment and develop a polynomial time scheduling algorithm that uses this relation. We show experimentally that the voltage assignment obtained by our algorithm is very close to that of the optimal assignment.

Design and analysis of low power Carbon Nanotube Field Effect Transistor (CNFET) D Flip-Flops (DFFs)

This paper presents design and analysis of D Flip-Flops (DFFs) using Carbon Nanotube Field-Effect Transistors (CNFETs). Two different DFF circuits are implemented. Circuit performance of CNFET models have been compared to silicon based CMOS models in terms of Clk-Q delay, average power, power delay product (PDP), setup time, hold time, minimum operating voltage, area and average leakage power. CNFET DFFs have shown superior performance over CMOS DFFs in simulations for all the performance parameters.

Application of very fast simulated reannealing (VFSR) to low power design

This paper addresses the problem of optimal supply and threshold voltage selection with device sizing by minimizing power consumption and maximizing battery charge capacitance using Very Fast Simulated Reannealing (VFSR). We assume that multiple supply voltages and multiple threshold voltage devices are available at gate level. Minimizing power consumption does not necessarily maximize battery charge capacitance. This paper achieves this by implementing both objectives in the cost function.

Voltage scaling for energy minimization with QoS constraints

We propose variable voltage scheduling algorithms that minimize energy while satisfying the quality of service (QoS) requirements. We consider the case when multiple applications are running on a single processor equipped with a limited sized buffer and each application has a different computational load and timing constraint. We use the Lagrange multiplier method to theoretically determine the relation between the application voltages such that the energy is minimum, and then develop iterative algorithms to satisfy the relation. The iterative algorithms find the minimum energy solution with polynomial time complexity for both the off-line case and the online case. We show the effect of buffer size and application deadline times on the ability of the system to reduce energy. Furthermore, we consider the effect of discharge current on battery life and show that the voltage assignment for maximum battery capacity is very similar to the voltage assignment for maximum energy.

Power-Aware L1 and L2 Caches for GPGPUs

General Purpose Graphics Processing Units (GPGPUs) employ several levels of memory to execute hundreds of threads concurrently. L1 and L2 caches are critical to performance of GPGPUs but they are extremely power hungry due to the large number of cores they need to serve. This paper focuses on power consumption of L1 data caches and L2 cache in GPGPUs and proposes two optimization techniques: the first optimization technique places idle cache blocks into drowsy state to reduce leakage power. Our evaluations show that cache blocks are idle for long intervals and putting them into drowsy mode immediately after each access reduces leakage power dramatically with negligible impact on performance. The second optimization technique reduces dynamic power of caches. In GPGPU applications, many warps have inactive threads due to branch divergence. Existing GPGPU architectures access cache blocks for both active and inactive threads, wasting power of caches. We use active mask of GPGPUs and access only the portion of cache blocks that are required by active threads. By dynamically disabling unnecessary sections of cache blocks, we are able to reduce dynamic power of caches significantly.

Optimum Buffer Size for Dynamic Voltage Processors

This paper addresses the problem of calculating optimum buffer size for a dynamic voltage scaling processor. We determine the minimum required buffer size giving minimum energy solution for periodic (single, multiple) or aperiodic tasks. The calculations are based on information about data size (maximum, minimum), execution time (best case, worst case), and deadlines.

Low-Power Low-Noise RF Amplifier for RFID Applications

A low-power low-noise amplifier (LNA) operating at 2.45 GHz has been designed for RFID applications. LNA provides a gain of about 14.5 dB, and a noise figure of 0.65 dB at the design frequency. Power consumption of LNA is measured as 6.5 mW and verified with Hspice.

Temperature aware datapath scheduling

This paper presents temperature aware low power scheduling under resource and latency constraints. We assume resources with different energy delay values are available. These resources are optimized in terms of energy for a certain delay, using variable supply voltage, multiple threshold voltages and sizing techniques. The proposed algorithms are based on temperature and power efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy scheduling when there is no temperature critical points. If a functional unit reaches a critical temperature, algorithm tries not to schedule any nodes in the data flow graph to high temperature resources, thus decrease the chip temperature. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 2 times the critical path delay and one of the resource temperature is critical the average power reduction is 50.8% and utilization of the hot resource is average 1%.