Ali Naderi

Temperature dependence of electrical characteristics of carbon nanotube field-effect transistors: a quantum simulation study

By developing a two-dimensional (2D) full quantum simulation, the attributes of carbon nanotube field-effect transistors (CNTFETs) in different temperatures have been comprehensively investigated. Simulations have been performed by employing the self-consistent solution of 2D Poisson-Schrodinger equations within the nonequilibrium Greens function (NEGF) formalism. Principal characteristics of CNTFETs such as current capability, drain conductance, transconductance, and subthreshold swing (SS) have been investigated. Simulation results present that as temperature raises from 250 to 500 K, the drain conductance and on-current of the CNTFET improved; meanwhile the on-/off-current ratio deteriorated due to faster growth in off-current. Also the effects of temperature on short channel effects (SCEs) such as drain-induced barrier lowering (DIBL) and threshold voltage roll-off have been studied. Results show that the subthreshold swing and DIBL parameters are almost linearly correlated, so the degradation of these parameters has the same origin and can be perfectly influenced by the temperature.

SDC-CNTFET: STEPWISE DOPING CHANNEL DESIGN IN CARBON NANOTUBE FIELD EFFECT TRANSISTORS FOR IMPROVING SHORT CHANNEL EFFECTS IMMUNITY

A novel carbon nanotube field-effect transistor with stepwise doping profile channel (SDC-CNTFET) is introduced for short-channel effects (SCEs) improvement. In SDC-CNTFET, the channel is divided into five sections of equal length. Impurity concentration was reduced from 0.8 nm-1 to zero from the source side to the drain side of the channel, with stepwise profile. The devices have been simulated by the self-consistent solution of two-dimensional (2D) Poisson–Schrodinger equations, within the nonequilibrium Greens function (NEGF) formalism. We demonstrate that the proposed structure for CNTFETs shows considerable improvement in device performance focusing on leakage current and ON–OFF current ratio. In addition, the investigation of SCEs for the proposed structure shows the improved drain-induced barrier lowering (DIBL) and subthreshold swing (SS). Moreover, we will prove that the proposed structure has acceptable performance at different values of channel impurity concentration in terms of delay and power-delay product (PDP). All these investigations introduce SDC-CNTFET as a more reliable device structure in short-channel regime.

Applicability of Artificial Neural Network and Nonlinear Regression to Predict Mechanical Properties of Equal Channel Angular Rolled Al5083 Sheets

EQUAL CHANNEL ANGULAR ROLLING (ECAR) IS A SEVERE PLASTIC DEFOR-MATION (SPD) PROCESS IN ORDER TO ACHIEVE ULTRAFINE-GRAINED (UFG) STRUCTURE. IN THIS PAPER, THE MECHANICAL PROPERTIES OF ECAR PROCESS USING ARTIFICIAL NEURAL NETWORK (ANN) AND NONLINEAR REGRESSION HAVE BEEN ILLUSTRATED. FOR THIS PURPOSE, A MULTILAYER PERCEPTRON (MLP) BASED FEED-FORWARD ANN HAS BEEN USED TO PREDICT THE MECHANICAL PROPERTIES OF ECARED AL5083 SHEETS. CHANNEL OBLIQUE ANGLE, NUMBER OF PASSES AND THE ROUTE OF FEEDING ARE CONSIDERED AS ANN INPUTS AND TENSILE STRENGTH, ELONGATION AND HARDNESS ARE CONSIDERED AS THE OUTPUTS OF ANN. IN ADDITION, THE RELATIONSHIP BETWEEN INPUT PARAMETERS AND MECHANICAL PROPERTIES WERE EXTRACTED SEPARATELY USING NONLINEAR REGRESSION METHOD. COMPARING THE OUTPUTS OF MODELS AND EXPERIMENTAL RESULTS SHOWS THAT MODELS USED IN THIS STUDY CAN PREDICT AND ESTIMATE MECHANICAL PROPERTIES APPROPRIATELY. WHERE, THE PERFORMANCE OF ANN MODEL IS BETTER THAN THE CORRELATIONS TO PREDICT MECHANICAL PROPERTIES. FINALLY, THE DEVELOPED OUTPUTS OF NEURAL NETWORK MODEL ARE USED TO ANALYZE THE EFFECTS OF INPUT PARAMETERS ON TENSILE STRENGTH, ELONGATION AND HARDNESS OF ECARED AL5083 SHEETS.

Correlation Between Structural Parameters and Mechanical Properties of Al5083 Sheets Processed by ECAR

In the paper, structural parameters and mechanical properties of Al5083 alloy sheet during equal channel angular rolling (ECAR) process and their relationship are studied. In order to evaluate the effect of ECAR process, Al5083 strips were subjected to the ECAR process for 1, 2, and 3 passes through the die channel angles 110°, 120°, and 130° at two routes. The effect of the process on the microstructural evolution of samples was investigated by means of x-ray diffraction and EBSD techniques. X-ray pattern has been analyzed using Rietveld method to compute structural parameters, including microstrain, average crystallite size, and dislocation density. The results showed that the dislocation density and microstrain were increased, and crystallite size was decreased during ECAR process. It was found that the behavior of variations in mechanical properties was in accordance with the dislocation density changes. This paper revealed that the increase in the strength of ECARed samples could be attributed to reduction in high-angle grain boundaries and the increase in dislocation density. Moreover, the yield strength estimated from Taylor equation was found in accordance very well with the experimentally measured yield strength of the samples.

Improvement in the performance of graphene nanoribbon p-i-n tunneling field effect transistors by applying lightly doped profile on drain region

In this paper, an efficient structure with lightly doped drain region is proposed for p-i-n graphene nanoribbon field effect transistors (LD-PIN-GNRFET). Self-consistent solution of Poisson and Schrodinger equation within Nonequilibrium Green’s function (NEGF) formalism has been employed to simulate the quantum transport of the devices. In proposed structure, source region is doped by constant doping density, channel is an intrinsic GNR, and drain region contains two parts with lightly and heavily doped doping distributions. The important challenge in tunneling devices is obtaining higher current ratio. Our simulations demonstrate that LD-PIN-GNRFET is a steep slope device which not only reduces the leakage current and current ratio but also enhances delay, power delay product, and cutoff frequency in comparison with conventional PIN GNRFETs with uniform distribution of impurity and with linear doping profile in drain region. Also, the device is able to operate in higher drain–source voltages due to the effectively reduced electric field at drain side. Briefly, the proposed structure can be considered as a more reliable device for low standby-power logic applications operating at higher voltages and upper cutoff frequencies.

SLD-MOSCNT: A new MOSCNT with step–linear doping profile in the source and drain regions

In this paper, a new structure, step–linear doping MOSCNT (SLD-MOSCNT), is proposed to improve the performance of basic MOSCNTs. The basic structure suffers from band to band tunneling (BTBT). We show that using SLD profile for source and drain regions increases the horizontal distance between valence and conduction bands at gate to source/drain junction which reduces BTBT probability. SLD performance is compared with other similar structures which have recently been proposed to reduce BTBT such as MOSCNT with lightly-doped drain and source (LDDS), and with double-light doping in source and drain regions (DLD). The obtained results using a nonequilibrium Green’s function (NEGF) method show that the SLD-MOSCNT has the lowest leakage current, power consumption and delay time, and the highest current ratio and voltage gain. The ambipolar conduction in the proposed structure is very low and can be neglected. In addition, these structures can improve short-channel effects. Also, the investigation of cutoff frequency of the different structures shows that the SLD has the highest cutoff frequency. Device performance has been investigated for gate length from 8 to 20 nm which demonstrates all discussions regarding the superiority of the proposed structure are also valid for different channel lengths. This improvement is more significant especially for channel length less than 12 nm. Therefore, the SLD can be considered as a candidate to be used in the applications with high speed and low power consumption.

Modeling double gate FinFETs by using artificial neural network

The minimum feature size of the transistors will be decreases in the future years as predicted by the international technology roadmap for semiconductors. Multi-gate FETs such as FinFETs have emerged as the most promising candidates to extend the CMOS scaling into the sub-25nm regime when considering the low scale effects is important for decreasing the scale. Solving and simulating the equations of these devices are so complicated and time consuming. In this paper we use RBF network for simulating the I-V characteristics of common symmetric multi gate FinFETs by using some BSIM-CMG data as a database for training. The results show a good agreement between RBF network and BSIM-CMG. The maximum error between BSIM-CMG and RBF is only 1%. The RBF is used for simulating or predicting I-V curve for different inputs without solving the complicated equations.