Ali Tombak

A Ferroelectric-Capacitor-Based Tunable Matching Network for Quad-Band Cellular Power Amplifiers

A tunable matching network (TMN) based on ferroelectric capacitors for cellular power-amplifier applications was designed, fabricated, and tested. When the matching network is operated for GSM850/900 frequency bands, the input impedance varied from 3.44-j1.87 to 3.55-j0.02 Omega with a power gain variation of -1.35 to -1.62 dB. When the circuit is operated for digital communication system/personal communication system/wideband code division multiple access frequency bands, the input impedance varied from 4.28-j0.06 to 4.31+j0.97 Omega with a power gain variation of -2.05 to -1.79 dB. The nonlinearity of the TMN was also characterized on an on-wafer load-pull system using a 1.95-GHz test signal with CDMA2000 and high-speed downlink packet access modulation strings

High-Efficiency Cellular Power Amplifiers Based on a Modified LDMOS Process on Bulk Silicon and Silicon-On-Insulator Substrates With Integrated Power Management Circuitry

An RF high-voltage CMOS technology is presented for cost-effective monolithic integration of cellular RF transmit functions. The technology integrates a modified LDMOS RF power transistor capable of nearly comparable linear and saturated RF power characteristics to GaAs solutions at cellular frequency bands. Measured results for multistage cellular power amplifier (PA) designs processed on bulk-Si and silicon-on-insulator on high-resistivity Si substrates (1 kΩ·cm ) are presented. The low-band multistage PA achieves greater than 60% power-added efficiency (PAE) with more than 35.5-dBm output power. The high-band PA achieves 45%-53% PAE across the band with greater than 33.4-dBm output power. Measured linearity performance is presented using an EDGE modulation source. A dc/dc buck converter was also integrated in the PA die as the power management circuitry. Measured results for the output power, PAE, and spurious emissions in the receive band while the dc/dc converter is biasing the PA and running at different modes are reported.

A Flip-Chip Silicon IPMOS Power Amplifier and a DC/DC Converter for GSM 850/900/1800/1900 MHz Systems

An LDMOS-based MOS device, called integrated power MOS (IPMOS), was developed to provide integration of high-performance reliable RF power devices with the rest of the front-end using flip-chip packaging. A 3-stage power amplifier (PA) die containing 1-8-30 and 1-8-40 mm wide IPMOS devices was designed for GSM 1800/1900 and GSM 850/900 MHz systems, respectively. The PA for GSM 850/900 achieved power added efficiencies (PAE) in the range of 54 to 62 % across the band with output power (Pout) ranging from 34.5 to 35.4 dBm when driven with input power (Pin) greater than 3 dBm. The PA for GSM 1800/1900 achieved PAEs in the range of 39 to 42 % with Pout ranging from 32.5 to 33.7 dBm when driven with Pin greater than 4 dBm. A DC/DC buck converter was also designed using the same process, and the bias to the PA for GSM 850/900 was applied through this converter. PAEs when Pin and DC/DC converter output voltage are varied were compared.

Integration of a cellular handset power amplifier and a DC/DC converter in a Silicon-On-Insulator (SOI) technology

A DC/DC buck converter was integrated with a cellular handset power amplifier (PA) in a silicon-on-insulator (SOI) technology. The technology was designed to allow integration of high-performance reliable RF power devices with the front-end. The power devices uses an LDMOS-based MOS device, called integrated power MOS (IPMOS). A 3-stage power amplifier was designed for GSM850/900 and DCS/PCS bands. The PA achieved typical power added efficiencies (PAE) greater than 60% with Pout ranging from 35.5 to 36.7 dBm at GSM850/900 MHz band, and it achieved typical PAEs in the range of 44 to 49 % with Pout ranging from 33.6 to 33.8 dBm at DCS/PCS band. The PAE was also measured when the DC/DC converter biased the PA. Up to 25-percentage-point improvement in the PAE was observed compared to the case where the output power was controlled by varying the input power. The spurious emissions in the transmit band and the receive band noise were also reported.

Design of High-Order Switches for Multimode Applications on a Silicon-on-Insulator Technology

A silicon-on-insulator (SOI) CMOS technology on high-resistivity silicon substrates is presented for the design of high-power switches for cellular and wireless local area network handset applications. A design methodology is introduced to design high-order switches for optimal insertion loss and isolation performance. Sources of nonlinearities in SOI switches are discussed. To the best of our knowledge, this work is the first demonstration of high-power switches on a high-resistivity SOI CMOS technology for high-volume cellular handset applications with adequate intermodulation and harmonic distortion performance. The design details and measurement results for a variety of RF switches with general-purpose input/output and mobile industry processor interface control interfaces, flip-chip/wire-bond packaging, and for various standards are discussed.

RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications

A single-pole double-throw novel switch device in0.18¹m SOI complementary metal-oxide semiconductor(CMOS) process is developed for 0.9 Ghz wireless GSMsystems. The layout of the device is optimized keeping inmind the parameters of interest for the RF switch. A subcircuitmodel, with the standard surface potential (PSP) modelas the intrinsic FET model along with the parasitic elementsis built to predict the Ron and Coff of the switch. Themeasured data agrees well with the model. The eight FETstacked switch achieved an Ron of 2.5 ohms and an Coff of180 fF.

Cellular antenna switches for multimode applications based on a Silicon-on-Insulator technology

A Silicon-on-Insulator (SOI) CMOS technology on high resistivity silicon substrates is presented for the design of cellular antenna switches. The design and measurement results for an SP9T cellular antenna switch based on this technology are presented. To the best of our knowledge, this is the first demonstration of an SP9T cellular antenna switch with adequate intermodulation and harmonic distortion performance on a high resistivity SOI CMOS technology.

Advances in SOI switched capacitors for 4G tunable antennas

In order to provide increasing data rates demanded by the consumer market, the 4G RF cellular front-end is becoming increasingly complex with numerous transmit and receive bands, the possibility of multiple antennas and new architectures which involves Uplink and Downlink carrier aggregation. Such new architectures present extreme challenges for conventional fixed band systems composed of PAs, switches and filters. Tunable technologies using RFCMOS SOI technology on high resistivity substrates are already being deployed in increasing numbers in todays advanced RF cellular handsets. This paper will present a discussion on RF topologies and architectures enabled by modern RFSOI technologies to solve the increasingly complex 4G RF front-end, including a discussion of the critical specifications needed in this application space.

An X-band low-cost phased array based on the extended resonance power dividing technique

Extended resonance phased arrays do not need a separate power splitter and phase shifters compared to conventional phased array systems, resulting in substantial reduction in the circuit complexity and cost. An improved circuit topology has been introduced, which simplifies the design of large and miniaturized phased arrays based on this technique. An X-band 8-antenna extended resonance phased array has been designed, fabricated and tested. The measured scan range was 18 degrees, and the sidelobe level was better than 10 dB.