Alihossein Sepahvand

Improved Design Optimization for High-Efficiency Matching Networks

Multistage matching networks are often utilized to provide voltage or current gains in resonant conversion applications, such as large conversion ratio power converters and wireless power transfer. In the conventional approach, each stage of a multistage matching network is designed to have a purely resistive input impedance and assumed to be loaded by a purely resistive load. This paper introduces an improved design optimization approach for multistage matching networks comprising L-section stages. The proposed design optimization approach explores the possibility of improvement in efficiency of the network by allowing the L-section stages to have complex input and load impedances. A new analytical framework is developed to determine the effective transformation ratio and efficiency of each stage for the case when input and load impedances may be complex. The method of Lagrange multipliers is used to determine the gain and impedance characteristics of each stage in the matching network that maximize overall efficiency. Compared with the conventional design approach for matching networks, the proposed approach achieves higher efficiency, resulting in loss reduction of up to 35% for a three-stage L-section matching network. The theoretical predictions are validated experimentally using a three-stage matching network designed for 1 MHz and 100 W operation.

High efficiency 20–400 MHz PWM converters using air-core inductors and monolithic power stages in a normally-off GaN process

This paper presents high efficiency dc-dc converters based on monolithic normally-off GaN half-bridge power stages with integrated gate drivers. A new gate driver circuitry is introduced, which enhances both the power stage efficiency and the converter overall efficiency. While using only n-type transistors in the GaN process, the proposed gate driver maintains low quiescent power consumption by emulating the complementary operation commonly employed in CMOS processes. Level shifting is accomplished using a bootstrap technique, with the bootstrap capacitor and the bootstrap diode integrated on the same chip. A family of monolithic GaN chips has been designed, targeting operation from up to 45 V, delivering up to 16 W of output power, and operating at 20-400 MHz switching frequencies. The GaN chips are verified in synchronous buck converters, demonstrating record peak power stage efficiencies of 95.0% at 20 MHz, 94.2% at 50 MHz, 93.2% at 100 MHz, 86.5% at 200 MHz, and 72.5% at 400 MHz.

Voltage regulation and efficiency optimization in a 100 MHz series resonant DC-DC converter

This paper describes a closed-loop regulated dual half-bridge series resonant dc-dc converter operated at up to 100 MHz switching frequency using GaN half-bridge stages with integrated gate drivers. A digital online efficiency optimization technique together with burst-mode control are developed and applied, to achieve output voltage regulation and efficiency improvements. An experimental prototype is designed and constructed to convert an input de voltage of 20 V to a 12 V output at 100 MHz switching frequency and up to 1.75 W of output power, with up to 82 % efficiency.

High power density impedance control network DC-DC converter utilizing an integrated magnetic structure

This paper introduces a high-power-density high-efficiency isolated dc-dc converter based on the impedance control network (ICN) resonant converter architecture. The ICN converter maintains very high efficiency by achieving zero voltage switching (ZVS) and near zero current switching (ZCS) across a wide range of input voltages, output voltages and output power. High power density is achieved by combining the three inductors of the ICN converter into a single integrated magnetic structure with two coupled windings. Power losses in this integrated magnetic structure are minimized using a finite element analysis (FEA) based design optimization approach. A prototype 550-W, 1-MHz ICN converter incorporating the integrated magnetic structure, designed to operate over an input voltage range of 36 V to 60 V and an output voltage range of 34 V to 55 V is built and tested. The prototyped ICN converter achieves a power density of 462 W/in3, a peak efficiency of 96.7% and maintains efficiencies above 94.8% across its entire operating range.

A high power density single-phase inverter using stacked switched capacitor energy buffer

This paper presents a high power density 2 kW single-phase inverter, with greater than 50 W/in3 power density and 90% line-cycle average efficiency. This performance is achieved through innovations in twice-line-frequency (120 Hz) energy buffering and high frequency dc-ac power conversion. The energy buffering function is performed using an advanced implementation of the recently proposed stacked switched capacitor (SSC) energy buffer architecture, and the dc-ac power conversion is performed using a soft-switching SiC-FET based converter, with a digital implementation of variable frequency constant peak current control.

High power transfer density and high efficiency 100 MHz capacitive wireless power transfer system

This paper introduces a very high frequency (VHF) capacitive wireless power transfer architecture capable of achieving very high power transfer densities and high efficiencies. High power density is achieved using an operating frequency of 100 MHz and through appropriate design of matching networks. High efficiency is achieved using a custom designed half-bridge GaN chip with integrated gate drivers. To validate performance of the proposed architecture, a prototype capacitive wireless power transfer system is built and tested. Experimental results demonstrate that the system transfers 2.5 W of power across a 1 pF capacitive interface at a very high power transfer density of 1.1 W/mm2, at close to 90% efficiency.

100 MHz isolated DC-DC resonant converter using spiral planar PCB transformer

This paper describes a very high frequency (VHF) isolated dc-dc resonant converter operating at 100 MHz switching frequency with a rated output power of 2 W. The power stage consists of two half-bridge GaN chips with integrated gate drivers, one operating as a dc-ac inverter on the primary side, the other operating as an ac-dc synchronous rectifier on the secondary side. Isolation is provided by a spiral planar printed circuit board (PCB) transformer designed and optimized using 3D finite element modeling (FEM) tools and radio-frequency (RF) circuit design software. Simulation and experimental results are presented for a prototype step-down converter operating from 20 V input voltage. Experimental results show a peak efficiency of 80.5% at 1.8 W output power.

Monolithic multilevel GaN converter for envelope tracking in RF power amplifiers

This paper presents a monolithic multilevel converter realized in a depletion-mode GaN process and intended to operate as a drain supply modulator (DSM) for high efficiency radio-frequency (RF) power amplifiers (PAs). The custom prototype chip includes a four-level power stage with on-chip integrated gate drivers and damping networks designed to mitigate effects of parasitics during output voltage level transitions. An optimization algorithm is described to maximize the drain supply system efficiency using the level voltages and a minimum switching interval as optimization variables. The monolithic multilevel chip is used to construct a four-level converter prototype. Experimental results are presented for tracking 8 MHz sine-wave and 10 MHz LTE envelope signals. The converter output voltage exhibits fast and well damped level-to-level transients. For the 10 MHz LTE envelope signal, the converter achieves greater than 97.3% power stage efficiency at 3.5 W average output power level.

Automotive LED driver based on high frequency zero voltage switching integrated magnetics Ćuk converter

This paper presents a high-frequency zero voltage switching (ZVS) integrated-magnetics Ćuk converter well-suited for automotive LED-driver applications. Input inductor, output inductor and the transformer are realized on a single magnetic structure, resulting in very low input and output current ripples, thus reducing EMI and the need for an output filter capacitor. Furthermore, the converter switching frequency is selected above the AM band to reduce radio frequency interference. Active-clamp snubbers are used to mitigate effects of the transformer leakage inductance. It is found that the active-clamp snubbers introduce substantial deviations in the steady-state operation of this converter when compared to a conventional Ćuk converter. A numerical analysis technique is introduced to quickly evaluate the steady state behavior including the effects of non-linear transistor output capacitances on ZVS transitions. A prototype 1.8 MHz Ćuk converter with integrated magnetics is designed, built and tested. The prototype converter supplies 0.5 A output current to a string of 1-to-10 LEDs. It achieves 89.6% peak powerstage efficiency, and maintains greater than 80% overall efficiency across the wide output voltage range.

Improved design optimization approach for high efficiency matching networks

Multistage matching networks are often utilized to provide voltage or current gains in applications such as wireless power transfer. Usually, each stage of a multistage matching network is designed to have a purely resistive input impedance and assumed to be loaded by a purely resistive load. This paper introduces an improved design optimization approach for multistage matching networks comprising L-section stages. The proposed design optimization approach explores the possibility of improvement in efficiency of the network by allowing intermediate stages to have complex input and load impedances. A new analytical framework is developed to determine the effective transformation ratio and efficiency of each stage for the case when input and load impedances may be complex. The method of Lagrange multipliers is used to determine the gain and impedance characteristics of each stage in the matching network that maximize overall efficiency. Compared with the conventional design approach for matching networks, the proposed approach achieves higher efficiency, resulting in loss reduction of up to 35% for a three-stage L-section matching network. The theoretical predictions are validated experimentally using a three-stage matching network designed for 10 MHz and 10 W operation.