Alistair A. McEwan

A Reliability Enhancement Mechanism for High-Assurance MLC Flash-Based Storage Systems

Solid State Devices (SDDs) are replacing mechanical data storage devices such as Hard Disk Drives (HDDs). On the other hand the data reliability in these systems is being questioned due to the fast growth in flash technology such as Multi-Level Cell (MLC). Recently it has been revealed that the Bit Error Rate (BER) increases exponentially in MLC flash memories as they experience more flash writes. Additionally RAID in flash-based storage systems has an inherent problem, that all flash devices should not reachend of life at the same time. Diff-RAID [2] overcomes the said problem. However, Diff-RAID mechanism suffers from drastic age-variation especially during the first few replacements, a problem that has been identified and addressed in this research. A new reliability enhancement mechanism for high-assurance MLC flash-based storage systems has been proposed here, and is compared with published Diff-RAID results. Our mechanism has shown promising results. In terms of convergence, the proposed scheme is 7 times faster. Furthermore, no single device crosses 66% of the age (i.e. max. erasure cycles), unlike the Diff-RAID where in the first few replacements, few devices reach 70-80% of age, which is great improvement in terms of data reliability.

Unifying theories of interrupts

The concept of an interrupt is one that appears across many paradigms, and used in many different areas. It may be used as a device to assist specifications to model failure, or to describe complex interactions between non co-operating components. It is frequently used in hardware to allow complex scheduling patterns. Although interrupts are ubiquitous in usage, the precise behaviour of a system incorporating interrupts can be difficult to reason about and predict. In this paper, a complete theory of the interrupt operator presented by Hoare in his original treatment of CSP is proposed. The semantics are given in the CSP model in Unifying Theories of Programming. New and existing algebraic laws are proposed and justified. The contribution of the paper is therefore a denotational semantics of an interrupt operator, and a collection of algebraic laws that assist in reasoning about systems incorporating interrupts.

Age distribution convergence mechanisms for flash based file systems

Solid state devices are common choices for data and systems storage in many high assurance application domains due to features such as no moving parts, shock/temperature resistance and low power consumption. On the other hand, they present new challenges in data reliability concerns. In multilevel cell NAND flash memories the bit error rate increases exponentially with reduced endurance limit as compared to single-level cell NAND flash memories. This can significantly reduce the data reliability and integrity of flash based storage systems. One solution to this is Redundant Array of Independent Disk (RAID) mechanisms. However these have an inherent problem as all flash memory chips wear out at the same time due to equal distribution of write operations. Recent solutions such as Diff-RAID partly solve this problem using uneven parity distribution mechanism, but suffer age-variation problems thereby decreasing the reliability of the array as well as increasing the cost. In this paper we present a fast age distribution convergence mechanism and page write control mechanism for a solid state device array. This mechanism solves the age convergence problem and uses fewer replacement devices. In the case of pure random write distribution the mechanism also saves page writes, thereby increasing the lifespan of each element in the array.

A fast age distribution convergence mechanism in an SSD array for highly reliable flash-based storage systems

SSDs are now popular choice for large data storage compared to HDDs due to their promising features such as no moving parts, shock/temperature resistance and low power etc. On the other hand the fast growth in flash technology brings major data reliability concerns which need to be addressed. In multi-level cell (MLC) NAND flashes the Bit Error Rate (BER) increases exponentially with reduced endurance limit as compare to single-level cell (SLC) NAND flashes. In future this trend can significantly decrease the data reliability of flash-based storage systems. On the basis of new RAID technique, Diff-RAID [1], we present a fast age distribution convergence mechanism in an SSD array which can be instantly boosted the reliability of a flash-based storage system. Our evaluation results suggest that the proposed approach can improve overall reliability up to 5% during initial couple of SSD replacement process compared to original Diff-RAID technique.

Reliability and performance enhancements for SSD RAID

Abstract NAND based solid state storage devices are almost ubiquitously used in safety-critical embedded devices, and recent advances have demonstrated RAID architectures specific to solid state storage devices resulting in increased data reliability, with architectural enhancements to solve the age convergence problem. However, these techniques require devices to be taken off-line while components are replaced—consequently these devices are of limited use in hard real time systems. There are further real time issues in that the conventional architectures ignore other characteristics of solid state devices such as garbage collection and meta data management. In this paper we investigate techniques that support the replacement of aged devices in the array in such a way that we provide continuous system reliability. We also improve the performance overhead of the reconstruction process using a novel data migration policy. The techniques are implemented and tested in a trace-driven simulator, and results demonstrate that average I/O response time is improved by up to 39% with improvement by up to 45% in its standard deviation, overheads in terms of device replacement time are negligible, and read performance is improved by an average of 8%.

An Embedded FTL for SSD RAID

Solid State Disk (SSD) storage systems are the storage medium of choice in modern embedded devices, and so the performance, lifespan, and reliability of these devices is an increasing issue in many application domains. Previous work has proposed adaptations to RAID architectures to render them suitable for SSD systems. However these solutions open a number of challenges such as wear-levelling across the array, efficient address translation and fast access times. In this paper we present an adaptation to the Flash Translation Layer of an SSD controller that offers firstly reliability enhancement under both sequential and random write patterns, secondly a forced random write technique that permits novel wear-levelling algorithms, thirdly a dynamic data allocation policy at page level, and fourthly the meta data storage mechanism by introducing non-volatile SRAM (nvSRAM) for mapping and caching data. Our experimental results show that this FTL design makes RAIDbased SDD storage systems more reliable regardless of workload characteristics. Our implementation in synthesizable Verilog is shown to be amenable to further investigations and experiments.

On-Line Device Replacement Techniques for SSD RAID

NAND flash memory solid state devices are widely used in many platforms including consumer electronics and safety-critical embedded systems because they offer high performance and reliability. In previous work, we have developed a novel RAID architecture for NAND flash that protects a system from data loss in the case of failure, or wear-out, of individual flash chips. These mechanisms permit the recovery of data onto a new replacement chip when a particular element in the array reaches its endurance limit -- however the use of this architecture in a hard real-time system is limited as the memory needs to be taken off-line while the replacement is actioned and so memory access times become non-deterministic with respect to time. Moreover, existing hard disk based online reconstruction mechanisms do not work well with solid state RAID as they are unable to exploit flash memory internal operations such as garbage collection and metadata management. In this paper we present techniques for replacing elements in the array that are approaching their wear-out level that does not involve taking the array off-line, thereby increasing system dependability by providing continuous system availability with higher I/O performance for hard real-time embedded applications. We have implemented these techniques in our FPGA-based SSD RAID controller. Our simulation results indicate that the run-time device replacement techniques improved the average I/O response time by 39% during replacement. Moreover, these techniques improve the write capability, and reduce the time needed to execute a replacement.

Towards tool support for design and safety analysis of high consequence arming systems using matlab

High consequence arming systems are designed to prevent unwanted external (or potentially internal) energy flowing to a critical component without intention. The hazard analysis of such systems can be a slow and difficult manual process, potentially repeated in various life-cycle phases or on multiple design options. This paper details a simulation tool under development at AWE to provide a fast and repeatable analysis process. The simulation generates a set of possible paths along which different energy types could potentially propagate through the system. Behaviour identified by the tool can support the design of the system and selection of an architecture providing assurance of safety whilst still providing reliability. We present an outline of the model development process, results from its use with a case study and demonstrate the advantages over manual analysis. A number of limitations of the current implementation are discussed, we then propose future work aimed at alleviating some of these issues.

Age Aware Pre-emptive Garbage Collection for SSD RAID

Abstract Flash-based storage systems offer high performance, robustness, and reliability for embedded applications; however the physical nature of flash memory means that there are limitations to its usage in high reliability applications. In previous work, we have developed RAID architectures and associated controller hardware that increase the reliability and lifespan of these storage systems. However, flash memory needs regular garbage collection and this presents two issues in a high reliability context. The first issue concerns response times as when a garbage collector is active, the flash memory cannot be used by the application layer. This non-determinism in terms of response is problematic in high reliability systems that require real-time guarantees. The second issue concerns lifespan of flash chips. If the garbage collector is allowed free rein over erase operations while garbage collecting, this affects management of the lifespan of each SSD in the array. In this paper we present an enhanced, dynamic, real-time garbage collection method for SSD RAID that does not ignore the strict age distribution management, while offering deterministic response times for access. Real-time efficiency is further improved by dynamically coordinating garbage collection across each device in the array. Our simulation results indicate that the dynamic garbage collection technique maintains the age distribution at a level that does not affect reliability of individual devices. This is evidences using various synthetic and realistic traces dominated by random I/O loads.

A real-time hot swapping technique for SSD RAID systems

NAND flash memory solid state devices are widely used in many platforms including consumer electronics and safety-critical embedded systems because they offer high performance and reliability. In previous work, we have developed a novel RAID architecture for NAND flash that protects a system from data loss in the case of failure, or wear-out, of individual flash chips. These mechanisms permit the recovery of data onto a new replacement chip when a particular element in the array reaches its endurance limit. However the use of this architecture in a hard real-time system is limited as the memory needs to be taken off-line while the replacement is actioned and so memory access times become non-deterministic with respect to time. In this paper we present a hot swapping technique for replacing elements in the array that are approaching their wear-out level that does not involve taking the array off-line - thereby increasing the systems availability and providing guaranteed response time. The result is that our hot-swapping architecture is more suited to applications with hard real-time constraints. We have implemented this technique in our FPGA-based SSD-aware RAID controller, complete with a metadata management framework to increase throughput and efficiency.