Allan L. Fisher

Unlocking the clubhouse: the Carnegie Mellon experience

In the fall of 1995, just seven of 95 students entering the undergraduate program in computer science at Carnegie Mellon University were women. In 2000, 54 of 130, or 42%, were women. What happened? This article presents a brief history of the transformation at Carnegie Mellons School of Computer Science, and the research project that lay behind it. A fuller discussion, set in an analysis of gender issues in computing from childhood through college, is found in our book, Unlocking the Clubhouse: Women in Computing [2].The story begins with a research study designed specifically to diagnose and find remedies for the gender gap in Carnegie Mellons undergraduate computer science program. Female enrollment had hovered below 10% for a number of years, and the fraction of women leaving the program was approximately twice that for men. In 1995, the Alfred P. Sloan Foundation funded our proposal for a two-year program, which was followed up two years later with a two-year extension. The goal was to understand the experiences and choices of both men and women with respect to studying computer science, and to design interventions that would involve more women.

Undergraduate women in computer science: experience, motivation and culture

For the past year, we have been studying the experiences of undergraduate women studying computer science at Carnegie Mellon University, with a specific eye toward understanding the influences and processes whereby they attach themselves to or detach themselves from the field. This report, midway through the two-year project, recaps the goals and methods of the study, reports on our progress and preliminary conclusions, and sketches our plans for the final year and the future beyond this particular project.

Computing the Hough transform on a scan line array processor (image processing)

A parallel algorithm for a line-finding Hough transform that runs on a linearly connected, SIMD (single-instruction, multiple-data-stream) vector of processors is described. The authors show that a high-precision transform, usually considered to be an expensive global operation, can be performed efficiently, in two to three times real time, with only local, communication on a long vector. The algorithm also illustrates a decomposition principle that has wide application in algorithm design for large linear arrays. A review of straight-line Hough transform implementations is also presented. >

Parallelizing complex scans and reductions

We present a method for automatically extracting parallel prefix programs from sequential loops, even in the presence of complicated conditional statements. Rather than searching for associative operators in the loop body directly, the method rests on the observation that functional composition itself is associative. Accordingly, we model the loop body as a multivalued function of multiple parameters, and look for a closed-form representation of arbitrary compositions of loop body instances. Careful analysis of conditionals allows this search to succeed in cases where existing automatic methods fail. The method has been implemented and used to generate code for the iWarp parallel computer.

Systolic Algorithms for Running Order Statistics in Signal and Image Processing

Median smoothing, a filtering technique with wide application in digital signal and image processing, involves replacing each sample in a grid with the median of the samples within some local neighborhood. As implemented on conventional computers, this operation is extremely expensive in both computation and communication resources. This paper defines the running order statistics (ROS) problem, a generalization of median smoothing. It then summarizes some of the issues involved in the design of special purpose devices implemented with very large scale integration (VLSI) technology. Finally, it presents algorithms designed for VLSI implementation which solve the ROS problem and are efficient with respect to hardware resources, computation time, and communication bandwidth.

Darwin: customizable resource management for value-added network services

The Internet is rapidly changing from a set of wires and switches that carry packets into a sophisticated infrastructure that delivers a set of complex value-added services to end users. Services can range from bit transport all the way up to distributed value-added services like video teleconferencing, virtual private networking, data mining, and distributed interactive simulations. Before such services can be supported in a general and dynamic manner, we have to develop appropriate resource management mechanisms. These resource management mechanisms must make it possible to identify and allocate resources that meet service or application requirements, support both isolation and controlled dynamic sharing of resources across services and applications sharing physical resources, and be customizable so services and applications can tailor resource usage to optimize their performance. The Darwin project has developed a set of customizable resource management mechanisms that support value-added services. We present and motivate these mechanisms, describe their implementation in a prototype system, and describe the results of a series of proof-of-concept experiments.

Architecture of the PSC-a programmable systolic chip

In recent years, many systolic algorithms have been proposed as solutions to computationally demanding problems in signal and image processing and other areas. Such algorithms exploit the regularity and parallelism of problems to achieve high performance and low I/O requirements. Since systolic algorithms generally consist of a few types of simple processors, or systolic cells, connected in a regular pattern, they are less expensive to design and implement than more general machines. This advantage is offset by the fact that a particular systolic system can generally be used only on a narrow set of problems, and thus design cost cannot be amortized over a large number of units. One way to approach this problem is to provide a programmable systolic chip (PSC), many copies of which can be connected and programmed to implement many systolic algorithms. The systolic environment, by virtue of its emphasis on continuous, regular flow of data and fairly simple per-cell processing, imposes new design requirements for programmable processors which are quite different from those found in a general-purpose system. This paper describes the CMU PSC, a single-chip microprocessor suitable for use in groups of tens or hundreds for the efficient implementation of a broad variety of systolic arrays. The processor has been fabricated in nMOS, and is undergoing testing.

Scan line array processors for image computation

This paper describes the scan line array processor (SLAP), a new architecture designed for high-performance yet low-cost image computation. A SLAP is a SIMD linear array of processors, and hence is easy to build and scales well with VLSI technology; yet appropriate special features and programming techniques make it efficient for a surprisingly wide variety of low and medium level computer vision tasks. We describe the basic SLAP concept and some of its variants, discuss a particular planned implementation, and indicate its performance on computer vision and other applications.

Design of the PSC: A Programmable Systolic Chip

The programmable systolic chip (PSC) is a high performance, special-purpose, single-chip microprocessor intended to be used in groups of tens or hundreds for the efficient implementation of a broad variety of systolic arrays. For implementing these systolic arrays, the PSC is expected to be at least an order of magnitude more efticient than conventional microprocessors, llie development of the PSC design, from initial concept to a silicon layout, took slightly less than a year, This project represents an integration of many disciplines including applications, algorithms, architecture, microprocessor design, and chip layout. This paper describes the goals of the project, tlie design process, major design features and current status.

Verifying pipelined hardware using symbolic logic simulation

A method is presented for automated verification of synchronous pipelined circuits, based on symbolic simulation and the well-known program verification concept of representation functions. The use of representation functions to allow straightforward formulation of readable and intuitive specifications is demonstrated, along with the use of a symbolic switch-level simulator to automatically prove that a circuit meets its specification. As an example, a systolic stack with more than 5000 transistors can be formally verified in a few minutes on a VAX 8800.<<ETX>>