Allan M. Hartstein

A silicon nanocrystals based memory

A new memory structure using threshold shifting from charge stored in nanocrystals of silicon (≊5nm in size) is described. The devices utilize direct tunneling and storage of electrons in the nanocrystals. The limited size and capacitance of the nanocrystals limit the numbers of stored electrons. Coulomb blockade effects may be important in these structures but are not necessary for their operation. The threshold shifts of 0.2–0.4 V with read and write times less than 100’s of a nanosecond at operating voltages below 2.5 V have been obtained experimentally. The retention times are measured in days and weeks, and the structures have been operated in an excess of 109 cycles without degradation in performance. This nanomemory exhibits characteristics necessary for high density and low power.

The optimum pipeline depth for a microprocessor

The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing architectural parameters affect the optimal pipeline length: the degree of instruction level parallelism (superscalar) decreases the optimal pipeline length, while the lack of pipeline stalls increases the optimal pipeline length. This theory is tested by analyzing the optimal pipeline length for 35 applications representing three classes of workloads. Trace tapes are collected from SPEC95 and SPEC2000 applications, traditional (legacy) database and on-line transaction processing (OLTP) applications, and modern (e. g. web) applications primarily written in Java and C++. The results show that there is a clear and significant difference in the optimal pipeline length between the SPEC workloads and both the legacy and modern applications. The SPEC applications, written in C, optimize to a shorter pipeline length than the legacy applications, largely written in assembler language, with relatively little overlap in the two distributions. Additionally, the optimal pipeline length distribution for the C++ and Java workloads overlaps with the legacy applications, suggesting similar workload characteristics. These results are explored across a wide range of superscalar processors, both in-order and out-of-order.

Identification of electron traps in thermal silicon dioxide films

The infrared absorption of thermal SiO2 has been measured using the attenuated total reflectance technique. The samples were subjected to various water diffusion and annealing treatments. Electron trapping was also measured in similar samples. The infrared measurements show the presence of SiH, SiOH, and H2O groups in the SiO2 films, particularly after H2O diffusion. Examination of both the infrared absorption results and the electron trapping results show that the electron trap with a cross section of 1×10−17 cm2 is associated with SiOH groups, and that the electron trap with a cross section of 2×10−18 cm2 is associated with H2O.

Optimum power/performance pipeline depth

The impact of pipeline length on both the power and performance of a microprocessor is explored both theoretically and by simulation. A theory is presented for a wide range of power/performance metrics, BIPS/sup m//W. The theory shows that the more important power is to the metric, the shorter the optimum pipeline length that results. For typical parameters neither BIPS/W nor BIPS/sup 2//W yield an optimum, i.e., a non-pipelined design is optimal. For BIPS/sup 3//W the optimum, averaged over all 55 workloads studied, occurs at a 22.5 FO4 design point, a 7 stage pipeline, but this value is highly dependent on the assumed growth in latch count with pipeline depth. As dynamic power grows, the optimal design point shifts to shorter pipelines. Clock gating pushes the optimum to deeper pipelines. Surprisingly, as leakage power grows, the optimum is also found to shift to deeper pipelines. The optimum pipeline depth varies for different classes of workloads: SPEC95 and SPEC2000 integer applications, traditional (legacy) database and on-line transaction processing applications, modern (e.g. Web) applications, and floating point applications.

Photon assisted tunneling from aluminum into silicon dioxide

Abstract Using argon and krypton lasers the photon assisted tunneling of electrons from aluminum into the SiO2 conduction band was observed for the first time. The data are found to be in excellent agreement with a simple model assuming an AlSiO2 barrier height of 3.15 eV and an electron effective mass in the SiO2 band-gap of 0.5m. The results are consistent with the conclusion that the classical image force barrier lowering does not contribute to tunneling. The technique is promising for the study of interface phenomena.

Observation of amorphous silicon regions in silicon‐rich silicon dioxide films

Raman scattering and optical transmission measurements have been made on chemically vapor‐deposited Si‐rich SiO2 films. The measurements show segregated regions of amorphous silicon in the as‐deposited films. Annealing the films at 1150 °C completely crystallizes the amorphous silicon. Annealing at lower temperatures produces films with both amorphous and crystalline regions.

Cache miss behavior: is it √2?

It has long been empirically observed that the cache miss rate decreased as a power law of cache size, where the power was approximately -1/2. In this paper, we examine the dependence of the cache miss rate on cache size both theoretically and through simulation. By combining the observed time dependence of the cache reference pattern with a statistical treatment of cache entry replacement, we predict that the cache miss rate should vary with cache size as an inverse power law for a first level cache. The exponent in the power law is directly related to the time dependence of cache references, and lies between -0.3 to -0.7. Results are presented for both direct mapped and set associative caches, and for various levels of the cache hierarchy. Our results demonstrate that the dependence of cache miss rate on cache size arises from the temporal dependence of the cache access pattern.

A metal‐oxide‐semiconductor field‐effect transistor with a 20‐nm channel length

We have fabricated a Si metal‐oxide‐semiconductor field‐effect transistor with a 20‐nm channel length using a novel step/edge technique. An Al gate is evaporated onto a step in the SiO2 gate oxide. A second Al gate, separated from the first by a plasma‐enhanced chemical‐vapor‐deposited SiO2 layer, provides inversion layer extensions of the source and drain contacts. Electrical conductance measurements indicate a channel length approximately equal to the fabricated gate length.

The optimum pipeline depth considering both power and performance

The impact of pipeline length on both the power and performance of a microprocessor is explored both by theory and by simulation. A theory is presented for a range of power/performance metrics, BIPSm/W. The theory shows that the more important power is to the metric, the shorter the optimum pipeline length that results. For typical parameters neither BIPS/W nor BIPS2/W yield an optimum, i.e., a non-pipelined design is optimal. For BIPS3/W the optimum, averaged over all 55 workloads studied, occurs at a 22.5 FO4 design point, a 7 stage pipeline, but this value is highly dependent on the assumed growth in latch count with pipeline depth. As dynamic power grows, the optimal design point shifts to shorter pipelines. Clock gating pushes the optimum to deeper pipelines. Surprisingly, as leakage power grows, the optimum is also found to shift to deeper pipelines. The optimum pipeline depth varies for different classes of workloads: SPEC95 and SPEC2000 integer applications, traditional (legacy) database and on-line transaction processing applications, modern (e. g. web) applications, and floating point applications.

Quantum interference in ultrashort channel length silicon metal‐oxide‐semiconductor field‐effect transistors

Silicon metal‐oxide‐semiconductor field‐effect transistors have been constructed, using a novel edge deposition technique, which have active channel lengths ranging from 7.7 to 124 nm. The electrical conductance of the devices, at temperatures below 4.2 K, shows oscillations which are attributed to quantum mechanical interference due to reflections from the device edges. Model calculations are in good agreement with the experiment.