Allen Leung

Static single assignment form for machine code

Static Single Assignment (SSA) is an effective intermediate representation in optimizing compilers. However, traditional SSA form and optimizations are not applicable to programs represented as native machine instructions because the use of dedicated registers imposed by calling conventions, the runtime system, and target architecture must be made explicit. We present a simple scheme for converting between programs in machine code and in SSA, such that references to dedicated physical registers in machine code are preserved. Our scheme ignores all output- and anti-dependences imposed by physical registers while a program is in SSA form, but inserts compensation code during machine code reconstruction if any naming requirements have been violated. By resolving all mismatches between the two representations in separate phases, we are able to utilize existing SSA algorithms unaltered to perform machine code optimizations.

Scheduling time-constrained instructions on pipelined processors

In this work we investigate the problem of scheduling instructions on idealized microprocessors with multiple pipelines, in the presence of precedence constraints, release-times, deadlines, and latency constraints. A latency of <italic>l<subscrpt>ij</subscrpt></italic> specifies that there must be at least <italic>l<subscrpt>ij</subscrpt></italic> time-steps between the completion time of instruction <italic>i</italic> and the start time of instruction <italic>j</italic>. A latency of <italic>l<subscrpt>ij</subscrpt></italic>=−1 can be used to specify that <italic>j</italic> may be scheduled concurrently with <italic>i</italic> but not earlier. We present a generic algorithm that runs in <italic>O</italic>(<italic>n</italic><supscrpt>2</supscrpt>log<italic>n</italic>α(<italic>n</italic>)+<italic>ne</italic>) time, given<italic>n</italic> instructions and <italic>e</italic> edges in the precedence DAG, where α(<italic>n</italic>) is the functional inverse of the Ackermann function. Our algorithm can be used to construct feasible schedules for various classes of instances, including instances with the following configurations: (1) one pipeline, with individual release-times and deadlines and where the latencies between instructions are restricted to 0 and 1; (2) <italic>m</italic> pipelines, with individual release-times and deadlines, and monotone-interval order precedences; (3) two pipelines with latencies of −1 or 0, and release-times and deadlines; (4) one pipeline, latencies of 0 or 1 and individual processing times that are at least one; (5) <italic>m</italic> pipelines, intree precedences, constant latencies, and deadlines; (6) <italic>m</italic> pipelines, outtree precedences, constant latencies, and release-times. For instances with deadlines, optimal schedules that minimize the maximal tardiness can be constructed using binary search, in <italic>O</italic>(log <italic>n</italic>) iterations of our algorithm. We obtain our results using backward scheduling, a very general relaxation method, which extends, unifies, and clarifies many previous results on instruction scheduling for pipelined and parallel machines.

TimeC: A Time Constraint Language for ILP Processor Compilation

Enabled by RISC technologies, low-cost commodity microprocessors are performing at ever increasing levels, significantly via instruction level parallelism (ILP). This in turn increases the opportunities for their use in a variety of day-to-day applications ranging from the simple control of appliances such as microwave ovens, to sophisticated systems for cabin control in modern aircraft. Indeed, “embedded” applications such as these represent segments in the computer industry with great potential for growth. However, this growth is currently impeded by the lack of robust optimizing compiler technologies that support the assured, rapid and inexpensive prototyping of real-time software in the context of microprocessors with ILP. In this paper we describe a novel notation, TimeC, for specifying timing constraints in programs, independent of the base language being used to develop the embedded application; TimeC specifications are language independent and can be instrumented into imperative and object-oriented languages non-intrusively. As we will show, the program synthesis problem that arise out of Time_tract specifications, a subset of TimeC, are always “tractable.” In contrast, a range of specification mechanisms proposed earlier yield substantially intractable synthesis questions, thereby limiting their potential utility. We will compare the tractability and related expressive power issues between TimeC and some of the extant mechanisms for specifying properties of timed programs.

A fast algorithm for scheduling time-constrained instructions on processors with ILP

Instruction scheduling is central to achieving performance in modern processors with instruction level parallelism (ILP). Classical work in this area has spanned the theoretical foundations of algorithms for instruction scheduling with provable optimality, as well as heuristic approaches with experimentally validated performance improvements. Typically, the theoretical foundations are developed in the context of basic-blocks of code. In this paper, we provide the theoretical foundations for scheduling basic-blocks of instructions with time-constraints, which can play an important role in compile-time ILP optimizations in embedded applications. We present an algorithm for scheduling unit-execution-time instructions on machines with multiple pipelines, in the presence of precedence constraints, release-times, deadlines, and latencies l/sub ij/ between any pairs of instructions i and j. Our algorithm runs in time O(n/sup 3//spl alpha/(n)), where /spl alpha/(n) is the functional inverse of the Ackermann function. It can be used construct feasible schedules for two classes of instances: (1) one pipeline and the latencies between instructions are restricted to the values of 0 and 1, and (2) arbitrary number of pipelines and monotone-interval order precedences. Our result can be seen as a natural extension of previous work on instruction scheduling for pipelined machines in the presence of deadlines.

Run-time versus compile-time instruction scheduling in superscalar (RISC) processors: performance and tradeoffs

The RISC revolution has spurred the development of processors with increasing degrees of instruction level parallelism (ILP). In order to realize the full potential of these processors, multiple instructions must continuously be issued and executed in a single cycle. Consequently, instruction scheduling plays a crucial role as an optimization in this context. While early attempts at instruction scheduling were limited to compile-time approaches, the current trends are aimed at providing dynamic support in hardware. In this paper, we present the results of a detailed comparative study of the performance advantages to be derived by the spectrum of instruction scheduling approaches: from limited basic-block schedulers in the compiler, to novel and aggressive schedulers in hardware. A significant portion of our experimental study via simulations, is devoted to understanding the performance advantages of run-time scheduling. Our results indicate it to be effective in extracting the ILP inherent to the program trace being scheduled, over a wide range of machine and program parameters. Furthermore, we also show that this effectiveness can be further enhanced by a simple basic-block scheduler in the compiler, which optimizes for the presence of the run-time scheduler in the target; current basic-block schedulers are not designed to take advantage of this feature. We demonstrate this fact by presenting a novel basic-block scheduling algorithm that is sensitive to the lookahead hardware in the target processor.

Mucinous tubular and spindle cell carcinoma of the kidney: Diagnosis by fine needle aspiration and review of the literature

Renal mucinous tubular and spindle cell carcinoma (MTSCC) was recently described as a distinct subtype of renal cell carcinoma (RCC) in the 2004 World Health Organization classification of kidney tumors. MTSCC is a rare low grade malignancy with < 100 cases reported in the literature. To the best of our knowledge, there are 5 case reports with a total of 6 patients describing its diagnosis by fine needle aspiration (FNA). All of these cases were diagnosed as conventional RCC on FNA. Subsequent excisions proved them to be MTSCC. We herein report a case in a 67-year-old male. He presented with abdominal pain and was found to have a new colon adenocarcinoma with metastasis to the liver and lungs. The extent of disease made the patient ineligible for surgical excision, and he received chemotherapy. Work-up also revealed a kidney mass which was later biopsied by FNA and core biopsy. The tumor was composed of epithelial and spindled cell components embedded in a myxoid background. It was positive for CK7, AMCAR, vimentin, and epithelial membrane antigen. The tumor was diagnosed as MTSCC. One year later the kidney mass remained stable. However, the patient developed new metastasis to the liver from colonic primary. The kidney mass was not resected. Although rarely encountered in FNA cytology of the kidney, we believe the cytologic features of this tumor are distinctive and are different from conventional and other subtypes of RCC. Therefore, its accurate diagnosis on FNA is possible once pathologists are aware that MTSCC should be considered in the differential diagnosis of kidney tumors.

Myositis ossificans within the intercondylar notch treated arthroscopically

We present a case of intraarticular myositis ossificans in the right knee of a child. Myositis ossificans (MO), though relatively rare in childhood and even more uncommon within a joint, should be included in the differential diagnosis of an intra-articular mass when indicated by the typical clinical, radiographic, and histologic findings. An 11-year-old male presented with a history of trauma to his right knee. Four weeks after the initial injury, an MRI demonstrated evidence of an ACL rupture with a “cystic mass” within the intercondylar notch along the anterior surface of the torn ligament. At subsequent arthroscopy, the mass noted on MRI was removed. The histology was consistent with MO. The authors believe this to be the first case of MO in the intercondylar notch detected by MRI, treated by arthroscopy, and confirmed by histology.

Self-clotting method improves cell block preparation: Clotting Improves Cell Block Preparation

The success of cell block preparation is crucial for ancillary diagnostic tests in cytology. However, achieving an optimal cell block can be challenging. The current study describes a self‐clotting‐based technique for fine‐needle aspiration (FNA) cell block preparations and evaluates its usefulness in comparison with the conventional needle wash technique.

Run-Time versus Compile-Time Instruction Scheduling in Superscalar (RISC) Processors

The RISC revolution has spurred the development of processors with increasing degrees ofinstruction level parallelism(ILP). In order to realize the full potential of these processors, multiple instructions must continuously be issued and executed in a single cycle. Consequently,instruction schedulingplays a crucial role as an optimization in this context. While early attempts at instruction scheduling were limited to compile-time approaches, the current trends are aimed at providingdynamicsupport in hardware. In this paper, we present the results of a detailed comparative study of the performance advantages to be derived by the spectrum of instruction scheduling approaches: from limited basic-block schedulers in the compiler, to novel and aggressive schedulers in hardware. A significant portion of our experimental study via simulations, is devoted to understanding the performance advantages of run-time scheduling. Our results indicate it to be effective in extracting the ILP inherent to the program trace being scheduled, over a wide range of machine and program parameters. Furthermore, we also show that this effectiveness can be further enhanced by a simple basic-block scheduler in the compiler, which optimizes for the presence of the run-time scheduler in the target; current basic-block schedulers are not designed to take advantage of this feature. We demonstrate this fact by presenting a novel basic-block scheduling algorithm that is sensitive to the lookahead hardware in the target processor. Finally, we outline a simple analytical characterization of the performance advantage that run-time schedulers have to offer.

Chondroid syringoma of the axilla: An unusual tumor diagnosed by fine needle aspiration

Chondroid syringoma (CS) is a rare benign adnexal tumor of the skin with a resemblance to pleomorphic adenoma of salivary gland, most commonly involving the head and neck region. In the present literature, reports of the cytologic appearance of CS are scarce as it is rarely encountered by fine needle aspiration (FNA). A 67‐year‐old woman presented with a 1 year history of a 1 cm subcutaneous nodule in the right axilla. FNA biopsy was performed revealing an epithelial–mesenchymal biphasic neoplasm suggesting CS. Surgical excision confirmed the diagnosis and demonstrated extensive ossification, an extremely rare feature, with only seven reported cases, all located on the head. CS is a rare benign adnexal tumor of the skin, often overlooked due to its unremarkable clinical presentation. FNA is a reliable tool for the diagnosis of CS and helps guide optimal surgical management. Diagn. Cytopathol. 2016;44:342–346.