Allen M. Dewey

Virtual enterprise and emissary computing technology

Integrated product teaming, concurrent engineering, supply-chain management, and build-to-order manufacturing are all examples of the growing interest in collective business engagements involving interorganizational collaboration. The pressing need to automate interorganizational collaboration is motivating the emergence of virtual enterprise technology to enable the rapid formation, execution, and dissolution of joint ventures within the confines of an information infrastructure supporting electronic data interchange and commerce. Virtual enterprise technology, in turn, is creating the need for new high-performance computation and communication strategies. Collectively known as emissary computing, these strategies use highly empowered servers called emissaries to represent and interconnect organizations participating in a joint business engagement. Emissary computing addresses organizational interactions and can be viewed as an extension of proxy computing that addresses more simple resource interactions (e.g., communication gateways, Web servers). Virtual enterprises and emissary computing are establishing new directions in information-processing architectures and paradigms, and form key enabling technologies for interorganizational collaboration.

Manufacturing virtual enterprises through the use of the National Industrial Information Infrastructure Protocols (NIIIP)

Manufacturing plays a central role in successfully competing in international markets. Improving a companys manufacturing capability and, consequently its posture in global markets, requires that the company respond more rapidly to market opportunities. The rate at which new product ideas mature to commodity status is increasing, resulting in a growing emphasis on time-to-market as a key competitive differentiator. Realizing these new efficiencies in product development requires that organizations interconnect, software systems interoperate, and individuals interact. These challenges are being addressed by the National Industrial Information Infrastructure Protocols (NIIIP) Consortium in its work to define and develop virtual enterprise technology. This paper presents an overview of NIIIP technology and discusses a program deploying NIIIP technology to establish new standards for integrating manufacturing applications, focusing on manufacturing execution systems.

Applicability of discrete event hardware description languages to the design and documentation of electronic analog systems

This chapter investigates the applicability of discrete event hardware description languages (HDLs), in general, and VHDL, in particular, to the design and documentation of analog electronic systems. The study focuses on the types of analog systems that can be modeled using IEEE 1076–1993 VHDL, without extensions to the language. To that end, data-sampled analog systems are defined and two subclasses of data-sampled analog systems are examined: network-independent and networkdependent behaviors. With respect to network-independent data-sampled analog systems, examples are presented of basic transformational descriptions, e.g., an operational amplifier, and more advanced discrete-convolution based descriptions, e.g., a lowpass filter. With respect to network-dependent data-sampled analog systems, examples of modeling loading effects and utilizing two-port network theory are presented. This work provides a perspective on the capabilities and limitations of discrete event hardware description languages in modeling analog or continuous event behavior. The classes of analog systems investigated illustrate present modeling technology and suggest directions for future applications of emerging analog modeling languages.

A DSP Prediction Methodology

The objective of this chapter is to illustrate the application of the general prediction methodology concepts discussed in Section 3.2 by explaining how the implementation performance predictions are obtained for the case of digital filter design. Based on the initial functional specifications and a high-level roadmap for how the design is to proceed, i.e., the design plan, we seek to predict the eventual implementation performance.

Yoda: Sample Planning Session

The objective of this chapter is to bring together the general VLSI System Planning concepts discussed in Chapters 1 through 4 and the specific details of the digital signal processing planner discussed in Chapters 5 and 6 by presenting a sample planning session with Yoda. The discussion of the sample planning session will be supported by figures illustrating the content of the terminal screen. In this manner, some “user-oriented” features of Yoda will also be explained. It should be noted that the figures illustrating the terminal screen are intended to convey the general nature of the Mx display. Hence, the figures do not include all the details of the screen about the various menus and windows.

A DSP VLSI System Planner

In essence, the VLSI System Planning methodology acts as a framework for formalizing the decision-making process of design[105]. In the previous chapters we explained the methodology by presenting several design examples, such as an analog-to-digital converter, a memory subsystem, a finite state machine, an analog amplifier, etc. The objective of this chapter is to present in more detail the application of the VLSI System Planning methodology to the task of designing digital signal processing (DSP) filters. There are two reasons for presenting this example. The first reason is to show how the complex and diverse facets of digital filter design can be enumerated and consolidated into a more organized and logical process by using the VLSI System Planning methodology. Secondly, in a broader context, the digital filter design application is also intented to convey the “mindset”, or line of reasoning, involved in studying a design process, modeling the process as a hierarchy of design issues, delineating the options, and identifying the associated interdependencies and discriminating characteristics so that the reader may apply the VLSI System Planning methodology to his particular design task of Table 5.1 Digital Filter Design Issues Design Issues 1 Filter Algorithms 2 Filter Architectures 3 Multiplier Logic Designs 4 Adder Logic Designs 5 Layout Design Styles 6 Fabrication Technologies interest.

General Software Architecture

Having discussed the general VLSI System Planning methodology in Chapters 2 and 3, we now discuss the software architecture required to automate the methodology. This chapter will focus on the salient features from a conceptual or functional point of view. Supporting details on how the features are implemented are given in Appendix B.