Aloke Guha

Optical interconnections for massively parallel architectures

This paper presents a study of board-level interconnection requirements for highly parallel and massively parallel computing. Analytical models of the I/O bandwidth of popular interconnection networks have been developed and show that current electronic technologies are poor in supporting the necessary I/O density and bandwidth. Optical interconnects appear to offer greater potential in meeting these I/O requirements. Several possible optical implementations of interconnecting a network of electronic processors are compared. The use of polymer waveguides appears to offer the best solution compatible with existing multiboard system architectures.

Polymer Waveguide-Based Optical Backplane for Fine-Grained Computing

The interconnection requirements of fine-grained computing are examined and compared to the requirements of coarser grained, multiplexed systems. Specifications for the interconnection medium are developed and compared to the performance of available optical source and interconnection components. The use of polyimide waveguides for both applications is considered and the probable architecture of a multiboard fine-grained system is described.

Experimental evaluation of real-time support on the Mercuri wide area ATM testbed

ATM has been widely accepted as the key enabling technology for emerging multimedia applications. We at the Honeywell Technology Center are investigating the application of this technology to real-time control systems. The Mercuri wide area ATM testbed is a collaborative research effort in this direction. In this paper we describe our experiences from a series of performance evaluation experiments on the Mercuri testbed. Besides measuring application level throughput and round-trip delay, we investigated the support for real-time provisions like priority and deadline guarantees, which are especially important for control applications. We also measured delay and jitter for remote video transfer under no-load and loaded conditions. The major conclusion of our experiments is that the end systems remain a major bottleneck for high speed communications. We point out possible causes of performance degradation in this paper and outline some issues that need to be resolved for ATM to become a viable alternative for real-time multimedia based control applications.

Design Considerations For An Optical Symbolic Processing Architecture

We examine the key issues in designing an optical expert system architecture. Our conclusions, however, are extendable to architectures for supporting traditional symbolic processing. To determine the basic operations necessary for constructing an expert system, we examine the underlying symbolic processing languages and their associated computational models. We show that traditional symbolic processing in optics would require efficient means of representing and manipulating complex structured data. This requirement necessitates a location-based addressable memory in optics. Based on the analyses of the computational models, we conclude that the architecture most feasible for optical implementation is that for a combinator graph reduction computational model. We briefly outline a proposed fine-grained optical architecture for this computational model.

Continuous process control using neural networks

We present some adaptive control strategies based on neural networks that can be used for designing controllers for continuous process control problems. Specifically, a learning algorithm has been formulated based on reinforcement learning, a weakly supervised learning technique, to solve set-point control and control scheduling for continuous processes where the process cannot be modeled easily. It is shown how reinforcement learning can be used to learn the control strategy adaptively based on exploration of the control space without making assumptions about the process model. A new learning scheme, ‘handicapped learning’, was developed to learn a control schedule that specifies a schedule of set points. Applications studied include the control of a nonisothermal continuously stirred tank reactor at its unstable state and the learning of the daily time-temperature schedule for an environment controller. Experimental results demonstrate good learning performance, indicating that the learning algorithm can be used for solving transient startup and boundary value control problems.

Relating the cyclic behavior of linear and intrainverted feedback shift registers

Feedback shift registers (FSRs) are sometimes implemented with inversions between stages to improve their testability and their ability to locate faults. These intrainverted FSRs (IFSRs) can be realized with less overhead than standard linear feedback shift registers (LFSRs). It is shown how to relate the cyclic behavior of the LFSR and the corresponding IFSR, based on the same feedback polynomial, so that IFSRs can be designed to exploit the inherent implementation advantages while exhibiting the well-known behavior of LFSRs. In particular, it is shown that the cyclic and serial output behavior of LFSRs can be emulated by IFSRs when loaded with the appropriate initial states for most feedback shift register lengths and feedback polynomials. How the initial state for the IFSR can be derived, given the feedback polynomial and the initial state of the desired cycle in the LFSR, is described. Conditions under which such mapping of behavior cannot be guaranteed are given. >

Designing Optical Networks from Simple Switching Elements

An analysis of switching networks and current optical technology reveals that the topology of networks determines the extent to which optics can offer system-level performance advantages over electronic and electrical implementations. For direct connection networks such as mesh networks, hybrid electrooptical networks that employ circuit switching can reduce latency and thereby system throughput by an order of magnitude. For packet switched local area networks, optically controlled electrooptic waveguide crossbar networks provide higher efficiency and also lower latency advantages. To illustrate our thesis, we present two examples of electrooptical waveguide-based network designs. In the first, we describe a new self-routing optical crossbar design, VIPER +, that can be realized by locally controlled 2 × 2 electrooptic switches. The VIPER + crossbar is unique in that it can solve the network access and conflict arbitration problems optoelectronically. Further, by cascading the proposed crossbar networks, larger nonblocking self-routing optical networks can be implemented in modular fashion. The second design based on VIPER + is a waveguide mesh interconnection network that incorporates an optical express router, in which optical channels are accessed for remote processor communications, in an electrical mesh.

Designing massively parallel optical computers: a case study

This paper presents a case study in the design and analysis of a massively parallel optical computer, SPARO, a novel scalable computer intended for symbolic and numeric computing. SPARO was designed for fine-grained parallel processing of combinator graph reduction, a special case of the graph reduction computational model, found most appropriate for parallel optical processing in earlier studies. The architecture consists of a planar array of optical processors that communicate through simple messages (data packets) over an optical interconnection network. A technique called instruction passing is used to realize distributed control of the architecture. Instruction passing can also be used to implement complex structures such as recursion and iteration. Each individual processor in SPARO is a finite state machine that is implemented using symbolic substitution techniques, while gateable interconnects are used to realize data movements between the processors and network. Performance analysis of SPARO reveals that while discrete computing structures can be implemented using optical techniques, massively parallel optical architectures for traditional computational models are currently unable to compete with electronic ones due to the lack of large scale addressable optical memory devices and large scale integratable optical computing elements. However, optical interconnections appear very promising for providing the network throughput necessary for these parallel architectures.

Architectural issues in designing symbolic processors in optics

This paper analyzes potential optical architectures for AI applications (such as knowledge-based systems). Our goal was to investigate architectures most suitable for implementation completely in optics. While optical computing appears to hold much promise because of its inherent parallelism and speed, constructing a symbolic processor or even a general purpose computer in optics requires examining many issues never before addressed. This paper presents these issues and discusses those architectures which appear most feasible in optics. We take into account fundamental physical limitations as well as the state-of-the-art optical device research. We conclude that, unlike in electronics, large-grained parallelism is not suitable for implementation in optics. We also find that functional languages, rather than logic languages, are better candidates for optics. Finally, we show that implementing an optical symbolic processor warrants the need for a real, or at least an emulated, addressable memory in optics.

A scalable packet switch for distributed computing

To address the growing demands of distributed computing, the authors propose a new switch architecture called VIPER+ that is based on a self-routing nonblocking network design. VIPER+ can be designed from simple 2*2 switching elements, either electrical or photonic. The self-routing properties of the switch enable scalability with the technology of the switching devices employed. The switch architecture, targeted for optical implementation, relies on simpledistributed routing algorithms and uses cut-through switching to avoid buffering at the switch interface. The authors outline the switch architecture using VIPER+, and the projected performance based on analytical modeling.<<ETX>>