Alpana Agarwal

Digital background calibration of charge pump based pipelined ADC

ABSTRACT In the presented work, digital background calibration of a charge pump based pipelined ADC is presented. A 10-bit 100 MS/s pipelined ADC is designed using TSMC 0.18 µm CMOS technology operating on a 1.8 V power supply voltage. A power efficient opamp-less charge pump based technique is chosen to achieve the desired stage voltage gain of 2 and digital background calibration is used to calibrate the inter-stage gain error. After calibration, the ADC achieves an SNDR of 66.78 dB and SFDR of 79.3 dB. Also, DNL improves to +0.6/–0.4 LSB and INL improves from +9.3/–9.6 LSB to within ±0.5 LSB, consuming 16.53 mW of power.

Carry circuitry for LUT-based FPGA

This paper presents a carry chain design optimized for implementing multipliers along with the adder circuitry. This kind of architecture will be very useful for designs which have very large number of mathematical operations in it. The aim of the architecture is to accommodate as much logic as possible in one LUT without increasing the size of the LUT proportionately. The discussed carry chain design is compatible with both 3-input as well as 4-input LUTs. The paper ends with a comparative study of multiplier implementation on various popular FPGA architectures.

Figure-of-merit-based area-constrained design of differential amplifiers

A new methodology based on the concept of figure of merit under area constraints is described for designing optimum performance dierential amplifiers. First a figure of merit is introduced that includes the three performance parameters, namely, input-referred noise, dierential dc gain, and unity-gain bandwidth. Expressions for these parameters have been derived analytically and finally arrived at an expression for the figure of merit. Next it is shown how these performance parameters vary with the relative allocation of the total available area between the input and load transistors. The figure of merit peaks at a certain value of relative area allocation in the range of 60% to 80% of the available area to the input transistors. The peak value of figure of merit is a function of area. However, it is independent of biasing current (and, therefore, power consumption) subject to the minimum current (and, therefore, a minimum power) required to keep all the transistors biased in the saturation region. The peak figure of merit and minimum power required to achieve the peak figure of merit are also plotted as a function of area. These analyses help in synthesizing optimal dierential amplifier circuit designs under area constraints.

Power and Area Efficient Pipelined ADC Stage in Digital CMOS Technology

ABSTRACT A power and area efficient metal-oxide semiconductor field-effect transistor (MOSFET)-only 1.5-bit fully differential pipelined analog-to-digital converter (ADC) stage is proposed and designed in TSMC 0.18 μm digital CMOS technology with supply voltage of 1.8 V. It is based on charge pump based technique to achieve the stage voltage gain of 2. Various capacitances are implemented by MOSCAPs (capacitance offered by the MOSFET), offering compatibility with cheaper digital complimentary metal-oxide semiconductor (CMOS) process in order to reduce the much required manufacturing cost. The proposed stage suffers from only linear gain error with full signal swing of 2 V peak-to-peak (p–p) differential. Using the proposed stage, un-calibrated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) for 10-bit, 100 MS/s pipelined ADC are 40.11 and 40.86 dB, respectively, which can be further increased by using a simple digital calibration technique. Comparison between the proposed stage and conventional operational amplifier based stage shows insensitivity towards capacitor mismatch along with power savings and design simplicity.

Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

ABSTRACT A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

Genetic algorithm for ordering and reduction of BDDs for MIMO circuits

Boolean function manipulation is an important component of many logic synthesis algorithms including logic optimization and logic verification of combinational and sequential circuits. Digital integrated circuits, often represented as Boolean functions, can be best-manipulated graphically in the form of Binary Decision Diagrams (BDD). Reduced-ordered binary decision diagrams (ROBDDs) are data structures for representation and manipulation of Boolean functions. The variable ordering largely influences the size of the BDD, varying from linear to exponential. In this paper, an evolutionary algorithm named genetic algorithm has been proposed for minimization of shared ordered BDDs by finding the optimal input variable ordering that aims to minimize the node count using Genetic algorithm. The proposed algorithm gives upto 79% less nodes for LGSynth93 Benchmark Circuits.

A Highly-Digital Voltage Scalable 4-bit Flash ADC

This study describes the highly-digital 4-bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time-to-market and is scalable with technology. The comparators used in the ADC consist of complementary metal-oxide-semiconductor (CMOS)-based inverter and NAND-NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal-to-noise and distortion ratio, signal-to-noise ratio and spurious-free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non-linearity (DNL) of this ADC is ± 0.25 LSB and integral non-linearity (INL) is + 0.6 LSB.

A Digital-Based Low-Power Fully Differential Comparator

Low-power circuits are highly in demand in this power-hungry world of batteries and portable devices. Though many low-power techniques are prevalent at various stages of a VLSI design cycle, but most of them have retained their own domain. A novel, digital-in-concept, fully differential voltage comparator circuit has been implemented in this paper. This provides substantial reduction in the power consumption. It is highly cost-effective, both in terms of time and efforts as an analog circuit is being designed on digital basis. The proposed voltage comparator has been designed and simulated in Cadence® Virtuoso Analog Design Environment using UMC 180nm CMOS technology at 1.8V supply.

Low-power 10-bit 100 MS/s pipelined ADC in digital CMOS technology

A 10-bit pipelined analogue-to-digital converter (ADC) at a sampling rate of 100 MS/s utilising only metal–oxide–semiconductor (MOS) transistors is presented and designed in 1.8 V 0.18 μm standard digital complementary MOS (CMOS) n-well technology. The internal gain of value 2 of the intermediate stages is achieved by using a charge-pump-based concept that avoids the use of power-area inefficient operational amplifier. All the capacitors are realised by capacitors implemented by metal–oxide–semiconductor field-effect transistors (MOSCAPs) that allows easy integration with any inexpensive standard digital CMOS technology, and altogether giving low area-power-cost solution. A low DC gain CMOS differential amplifier in source follower configuration is used and low gain effects are calibrated digitally in the background. Peak differential non-linearity (DNL) improves from −1/+0.27 least significant bit (LSB) to −0.43/+0.57 LSB and peak integral non-linearity (INL) is reduced from −9.56/+9.3 LSB to within range of ±0.5 LSB after calibration. Also signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) increase to 65.4 and 72.08 dB, respectively, after calibration.

Research issues related to cryptography algorithms and key generation for smart grid: A survey

With advent of technology existing electrical grids are changed to smart grids which are effective power management, secure communication, reduced production cost and environment friendly. But, Smart Grid is complex hierarchy architecture. There are various stakeholders included. So, the biggest challenges are authentication and authorization. Secondly how to secure the communication lines from various cyber attacks. In this paper, a survey is done on various cryptography algorithms and related key generation for smart grid application. On the basis of survey several research issue have been discussed for the secure operations in the smart grids. It has been found that lightweight algorithms are more suitable in smart meters because of less area and memory required. Key generation for cryptography algorithm should be generated from noise and jitter as a seed because of their random nature to prevent from cyber attacks.